mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformInitLib: Add hob functions
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 In this patch of PlatformInitLib, below hob functions are introduced: - PlatformAddIoMemoryBaseSizeHob - PlatformAddIoMemoryRangeHob - PlatformAddMemoryBaseSizeHob - PlatformAddMemoryRangeHob - PlatformAddReservedMemoryBaseSizeHob They correspond the below functions in OvmfPkg/PlatformPei: - AddIoMemoryBaseSizeHob - AddIoMemoryRangeHob - AddMemoryBaseSizeHob - AddMemoryRangeHob - AddReservedMemoryBaseSizeHob After above hob functions are introduced in PlatformInitLib, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
This commit is contained in:
parent
57bcfc3b06
commit
102cafedad
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@ -96,4 +96,40 @@ PlatformDebugDumpCmos (
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VOID
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);
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VOID
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EFIAPI
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PlatformAddIoMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize
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);
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VOID
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EFIAPI
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PlatformAddIoMemoryRangeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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EFIAPI
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PlatformAddMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize
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);
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VOID
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EFIAPI
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PlatformAddMemoryRangeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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EFIAPI
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PlatformAddReservedMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize,
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IN BOOLEAN Cacheable
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);
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#endif // PLATFORM_INIT_LIB_H_
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@ -0,0 +1,106 @@
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/**@file
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseMemoryLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/PlatformInitLib.h>
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VOID
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EFIAPI
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PlatformAddIoMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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EFIAPI
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PlatformAddReservedMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize,
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IN BOOLEAN Cacheable
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_RESERVED,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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(Cacheable ?
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
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0
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) |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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EFIAPI
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PlatformAddIoMemoryRangeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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EFIAPI
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PlatformAddMemoryBaseSizeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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EFIAPI
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PlatformAddMemoryRangeHob (
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IN EFI_PHYSICAL_ADDRESS MemoryBase,
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IN EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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@ -24,6 +24,7 @@
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[Sources]
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Cmos.c
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Platform.c
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[Packages]
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MdeModulePkg/MdeModulePkg.dec
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@ -34,3 +35,4 @@
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BaseLib
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DebugLib
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IoLib
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HobLib
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@ -275,10 +275,10 @@ ScanOrAdd64BitE820Ram (
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End = (E820Entry.BaseAddr + E820Entry.Length) &
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~(UINT64)EFI_PAGE_MASK;
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if (Base < End) {
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AddMemoryRangeHob (Base, End);
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PlatformAddMemoryRangeHob (Base, End);
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DEBUG ((
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DEBUG_VERBOSE,
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"%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
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"%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
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__FUNCTION__,
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Base,
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End
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@ -816,8 +816,8 @@ QemuInitializeRamBelow1gb (
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)
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{
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if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
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AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);
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AddReservedMemoryBaseSizeHob (
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PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);
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PlatformAddReservedMemoryBaseSizeHob (
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SMM_DEFAULT_SMBASE,
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MCH_DEFAULT_SMBASE_SIZE,
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TRUE /* Cacheable */
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@ -826,12 +826,12 @@ QemuInitializeRamBelow1gb (
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SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,
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"end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
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);
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AddMemoryRangeHob (
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PlatformAddMemoryRangeHob (
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SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,
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BASE_512KB + BASE_128KB
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);
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} else {
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AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
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PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
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}
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}
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@ -889,14 +889,14 @@ QemuInitializeRam (
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UINT32 TsegSize;
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TsegSize = mQ35TsegMbytes * SIZE_1MB;
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AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
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AddReservedMemoryBaseSizeHob (
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PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
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PlatformAddReservedMemoryBaseSizeHob (
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LowerMemorySize - TsegSize,
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TsegSize,
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TRUE
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);
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} else {
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AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
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PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize);
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}
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//
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@ -908,7 +908,7 @@ QemuInitializeRam (
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if (EFI_ERROR (Status)) {
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UpperMemorySize = GetSystemMemorySizeAbove4gb ();
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if (UpperMemorySize != 0) {
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AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
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PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
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}
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}
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}
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@ -57,85 +57,6 @@ BOOLEAN mS3Supported = FALSE;
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UINT32 mMaxCpuCount;
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_RESERVED,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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(Cacheable ?
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
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0
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) |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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MemMapInitialization (
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VOID
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@ -155,12 +76,12 @@ MemMapInitialization (
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//
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// Video memory + Legacy BIOS region
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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if (mHostBridgeDevId == 0xffff /* microvm */) {
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AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
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AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
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PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
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PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
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PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
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return;
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}
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@ -194,20 +115,20 @@ MemMapInitialization (
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// 0xFEE00000 LAPIC 1 MB
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//
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PciSize = 0xFC000000 - PciBase;
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AddIoMemoryBaseSizeHob (PciBase, PciSize);
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PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);
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PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
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ASSERT_RETURN_ERROR (PcdStatus);
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PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
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ASSERT_RETURN_ERROR (PcdStatus);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
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PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
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//
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// Note: there should be an
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//
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// AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
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// PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
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//
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// call below, just like the one above for RCBA. However, Linux insists
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// that the MMCONFIG area be marked in the E820 or UEFI memory map as
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@ -225,7 +146,7 @@ MemMapInitialization (
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// is most definitely not RAM; so, as an exception, cover it with
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// uncacheable reserved memory right here.
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//
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AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
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PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
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BuildMemoryAllocationHob (
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PciExBarBase,
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SIZE_256MB,
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@ -233,7 +154,7 @@ MemMapInitialization (
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);
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}
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AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
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PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
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//
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// On Q35, the IO Port space is available for PCI resource allocations from
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@ -11,37 +11,6 @@
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#include <IndustryStandard/E820.h>
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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);
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VOID
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AddressWidthInitialization (
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VOID
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