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ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory 

The VRAM of the PL111 on the FVP Base/Foundation models is described as
device memory rather than uncached memory, which is not an accurate
description of the nature of the region (i.e., a framebuffer), and may
result in problems when using accelerated string routines to access the
region, since this may legally involve unaligned accesses or DC ZVA
instructions, which are not allowed on device mappings.

So split of the 8 MB VRAM region into a separate region, and map it using
memory attributes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel 2017-04-06 14:05:12 +01:00
parent 7c410b3d41
commit 1344c8c605
2 changed files with 18 additions and 7 deletions
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11
ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
View File

@ -40,9 +40,11 @@
#define ARM_VE_SMB_SRAM_BASE 0x2E000000
#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
// USB, Ethernet, VRAM
#define ARM_VE_SMB_PERIPH_BASE 0x18000000
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
#define ARM_VE_SMB_PERIPH_BASE 0x18800000
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB)
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000
#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000
// DRAM
#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
@ -74,7 +76,4 @@
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
// VRAM offset for the PL111 Colour LCD Controller on the motherboard
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
#endif

14
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
View File

@ -21,7 +21,7 @@
#include <ArmPlatform.h>
// Number of Virtual Memory Map Descriptors
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
@ -130,6 +130,18 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// VRAM
VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;
//
// Map the VRAM region as Normal Non-Cacheable memory and not device memory,
// so that we can use the accelerated string routines that may use unaligned
// accesses or DC ZVA instructions. The enum identifier is slightly awkward
// here, but it maps to a memory type that allows buffering and reordering.
//
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// Map sparse memory region if present
if (HasSparseMemory) {
VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;