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The VRAM of the PL111 on the FVP Base/Foundation models is described as device memory rather than uncached memory, which is not an accurate description of the nature of the region (i.e., a framebuffer), and may result in problems when using accelerated string routines to access the region, since this may legally involve unaligned accesses or DC ZVA instructions, which are not allowed on device mappings. So split of the 8 MB VRAM region into a separate region, and map it using memory attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>