mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
https://bugzilla.tianocore.org/show_bug.cgi?id=277 All CPUs use the same MTRR settings. Move MTRR settings from a field in the PROCESSOR_SMM_DESCRIPTOR structure into a module global variable. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
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@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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// Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
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//
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UINT64 gSmiMtrrs[MTRR_NUMBER_OF_FIXED_MTRR + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
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MTRR_SETTINGS gSmiMtrrs;
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UINT64 gPhyMask;
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SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
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UINTN mSmmMpSyncDataSize;
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@ -283,20 +283,12 @@ ReplaceOSMtrrs (
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IN UINTN CpuIndex
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)
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{
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PROCESSOR_SMM_DESCRIPTOR *Psd;
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UINT64 *SmiMtrrs;
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MTRR_SETTINGS *BiosMtrr;
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Psd = (PROCESSOR_SMM_DESCRIPTOR*)(mCpuHotPlugData.SmBase[CpuIndex] + SMM_PSD_OFFSET);
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SmiMtrrs = (UINT64*)(UINTN)Psd->MtrrBaseMaskPtr;
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SmmCpuFeaturesDisableSmrr ();
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//
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// Replace all MTRRs registers
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//
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BiosMtrr = (MTRR_SETTINGS*)SmiMtrrs;
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MtrrSetAllMtrrs(BiosMtrr);
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MtrrSetAllMtrrs (&gSmiMtrrs);
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}
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/**
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@ -1379,7 +1371,6 @@ InitializeMpServiceData (
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{
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UINT32 Cr3;
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UINTN Index;
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MTRR_SETTINGS *Mtrr;
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PROCESSOR_SMM_DESCRIPTOR *Psd;
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UINT8 *GdtTssTables;
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UINTN GdtTableStepSize;
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@ -1442,9 +1433,8 @@ InitializeMpServiceData (
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//
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// Record current MTRR settings
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//
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ZeroMem(gSmiMtrrs, sizeof (gSmiMtrrs));
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Mtrr = (MTRR_SETTINGS*)gSmiMtrrs;
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MtrrGetAllMtrrs (Mtrr);
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ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs));
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MtrrGetAllMtrrs (&gSmiMtrrs);
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return Cr3;
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}
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@ -380,7 +380,7 @@ typedef struct {
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UINT16 Reserved11; // Offset 0x50
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UINT16 Reserved12; // Offset 0x52
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UINT32 Reserved13; // Offset 0x54
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UINT64 MtrrBaseMaskPtr; // Offset 0x58
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UINT64 Reserved14; // Offset 0x58
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} PROCESSOR_SMM_DESCRIPTOR;
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