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UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure

Browse Source 
https://bugzilla.tianocore.org/show_bug.cgi?id=277

All CPUs use the same MTRR settings.  Move MTRR settings
from a field in the PROCESSOR_SMM_DESCRIPTOR structure into
a module global variable.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Michael Kinney 2016-11-17 20:50:27 -08:00
parent 018c3c0b3e
commit 26ab5ac362
2 changed files with 5 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
// //
// Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE) // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
// //
UINT64 gSmiMtrrs[MTRR_NUMBER_OF_FIXED_MTRR + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; MTRR_SETTINGS gSmiMtrrs;
UINT64 gPhyMask; UINT64 gPhyMask;
SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL; SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
UINTN mSmmMpSyncDataSize; UINTN mSmmMpSyncDataSize;
@ -283,20 +283,12 @@ ReplaceOSMtrrs (
IN UINTN CpuIndex IN UINTN CpuIndex
) )
{ {
PROCESSOR_SMM_DESCRIPTOR *Psd;
UINT64 *SmiMtrrs;
MTRR_SETTINGS *BiosMtrr;
Psd = (PROCESSOR_SMM_DESCRIPTOR*)(mCpuHotPlugData.SmBase[CpuIndex] + SMM_PSD_OFFSET);
SmiMtrrs = (UINT64*)(UINTN)Psd->MtrrBaseMaskPtr;
SmmCpuFeaturesDisableSmrr (); SmmCpuFeaturesDisableSmrr ();
// //
// Replace all MTRRs registers // Replace all MTRRs registers
// //
BiosMtrr = (MTRR_SETTINGS*)SmiMtrrs; MtrrSetAllMtrrs (&gSmiMtrrs);
MtrrSetAllMtrrs(BiosMtrr);
} }
/** /**
@ -1379,7 +1371,6 @@ InitializeMpServiceData (
{ {
UINT32 Cr3; UINT32 Cr3;
UINTN Index; UINTN Index;
MTRR_SETTINGS *Mtrr;
PROCESSOR_SMM_DESCRIPTOR *Psd; PROCESSOR_SMM_DESCRIPTOR *Psd;
UINT8 *GdtTssTables; UINT8 *GdtTssTables;
UINTN GdtTableStepSize; UINTN GdtTableStepSize;
@ -1442,9 +1433,8 @@ InitializeMpServiceData (
// //
// Record current MTRR settings // Record current MTRR settings
// //
ZeroMem(gSmiMtrrs, sizeof (gSmiMtrrs)); ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs));
Mtrr = (MTRR_SETTINGS*)gSmiMtrrs; MtrrGetAllMtrrs (&gSmiMtrrs);
MtrrGetAllMtrrs (Mtrr);
return Cr3; return Cr3;
} }

2
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@ -380,7 +380,7 @@ typedef struct {
UINT16 Reserved11; // Offset 0x50 UINT16 Reserved11; // Offset 0x50
UINT16 Reserved12; // Offset 0x52 UINT16 Reserved12; // Offset 0x52
UINT32 Reserved13; // Offset 0x54 UINT32 Reserved13; // Offset 0x54
UINT64 MtrrBaseMaskPtr; // Offset 0x58 UINT64 Reserved14; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR; } PROCESSOR_SMM_DESCRIPTOR;