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MdeModulePkg/Xhci: Add 10ms delay before sending SendAddr cmd to dev 

We send ADDRESS DEVICE CMD in XhcInitializeDeviceSlot(), which will
cause XHC issue a USB SET_ADDRESS request to the USB Device.

According to USB spec, there should have a 10ms delay before this
operation after resetting a given port.

But in original code, there is a possible path which may have no such
10ms delay:
UsbHubResetPort()->UsbHubSetPortFeature()->Stall(20)->UsbHubGetPortSt
atus()->XhcPollPortStatusChange()->(if RESET_C bit is set)->
XhcInitializeDeviceSlot()->(if RESET_C bit is set)->Stall(10)

So this patch is used to fix above issue.

Cc: Star Zeng <star.zeng@intel.com>
Cc: Baraneedharan Anbazhagan <anbazhagan@hp.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Tested-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Feng Tian 2016-11-23 09:46:32 +08:00
parent 7fa1376c5c
commit 26b8501280
4 changed files with 31 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
View File

@ -2,7 +2,7 @@
Provides some data structure definitions used by the XHCI host controller driver.
Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -61,6 +61,11 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// XHC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//

10
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@ -2,7 +2,7 @@
XHCI transfer scheduling routines.
Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -2115,6 +2115,10 @@ XhcInitializeDeviceSlot (
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above.
//
// Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
// to device.
//
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
@ -2321,6 +2325,10 @@ XhcInitializeDeviceSlot64 (
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above.
//
// Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
// to device.
//
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);

8
MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
View File

@ -1,7 +1,7 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
@ -52,6 +52,12 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// Wait for root port state stable.
//

10
MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
View File

@ -2,7 +2,7 @@
PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
which is used to enable recovery function from USB Drivers.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
@ -1195,6 +1195,10 @@ XhcPeiInitializeDeviceSlot (
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above.
//
// Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
// to device.
//
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
@ -1402,6 +1406,10 @@ XhcPeiInitializeDeviceSlot64 (
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above.
//
// Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
// to device.
//
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);