ArmPkg/ArmGic: Disentangle ArmGicEnableDistributor () versions

Split ArmGicEnableDistributor () into GICv2 and v3 specific versions,
and move them into their single respective callers, so that the original
can be dropped from ArmGicLib altogether.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel 2025-01-16 16:35:25 +01:00 committed by mergify[bot]
parent 4e874fcf09
commit 2ab362f313
5 changed files with 25 additions and 44 deletions

View File

@ -15,7 +15,6 @@
[Sources]
ArmGicLib.c
ArmGicNonSecLib.c
GicV2/ArmGicV2Lib.c
GicV2/ArmGicV2NonSecLib.c

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@ -1,37 +0,0 @@
/** @file
*
* Copyright (c) 2011-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
VOID
EFIAPI
ArmGicEnableDistributor (
IN UINTN GicDistributorBase
)
{
ARM_GIC_ARCH_REVISION Revision;
UINT32 GicDistributorCtl;
/*
* Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented
*/
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
} else {
GicDistributorCtl = MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR);
if ((GicDistributorCtl & ARM_GIC_ICDDCR_ARE) != 0) {
MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2);
} else {
MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
}
}
}

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@ -389,6 +389,15 @@ GicV2SetTriggerType (
return EFI_SUCCESS;
}
STATIC
VOID
ArmGicEnableDistributor (
IN UINTN GicDistributorBase
)
{
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
}
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,

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@ -551,6 +551,22 @@ GicV3SetTriggerType (
return EFI_SUCCESS;
}
STATIC
VOID
ArmGicEnableDistributor (
IN UINTN GicDistributorBase
)
{
UINT32 GicDistributorCtl;
GicDistributorCtl = MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR);
if ((GicDistributorCtl & ARM_GIC_ICDDCR_ARE) != 0) {
MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2);
} else {
MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
}
}
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,

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@ -133,12 +133,6 @@ ArmGicSetSecureInterrupts (
IN UINTN GicSecureInterruptMaskSize
);
VOID
EFIAPI
ArmGicEnableDistributor (
IN UINTN GicDistributorBase
);
VOID
EFIAPI
ArmGicDisableDistributor (