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UefiCpuPkg: Use CET macro definitions in Cet.inc for SmiEntry.nasm files.

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Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Sheng Wei 2023-11-09 16:30:38 +08:00 committed by mergify[bot]
parent 04d47a9bf0
commit 3018685da8
2 changed files with 4 additions and 29 deletions
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16
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
@ -15,19 +15,7 @@
%include "StuffRsbNasm.inc" %include "StuffRsbNasm.inc"
%include "Nasm.inc" %include "Nasm.inc"
%include "Cet.inc"
%define MSR_IA32_S_CET 0x6A2
%define MSR_IA32_CET_SH_STK_EN 0x1
%define MSR_IA32_CET_WR_SHSTK_EN 0x2
%define MSR_IA32_CET_ENDBR_EN 0x4
%define MSR_IA32_CET_LEG_IW_EN 0x8
%define MSR_IA32_CET_NO_TRACK_EN 0x10
%define MSR_IA32_CET_SUPPRESS_DIS 0x20
%define MSR_IA32_CET_SUPPRESS 0x400
%define MSR_IA32_CET_TRACKER 0x800
%define MSR_IA32_PL0_SSP 0x6A4
%define CR4_CET 0x800000
%define MSR_IA32_MISC_ENABLE 0x1A0 %define MSR_IA32_MISC_ENABLE 0x1A0
%define MSR_EFER 0xc0000080 %define MSR_EFER 0xc0000080

17
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
@ -15,25 +15,12 @@
%include "StuffRsbNasm.inc" %include "StuffRsbNasm.inc"
%include "Nasm.inc" %include "Nasm.inc"
%include "Cet.inc"
; ;
; Variables referenced by C code ; Variables referenced by C code
; ;
%define MSR_IA32_S_CET 0x6A2
%define MSR_IA32_CET_SH_STK_EN 0x1
%define MSR_IA32_CET_WR_SHSTK_EN 0x2
%define MSR_IA32_CET_ENDBR_EN 0x4
%define MSR_IA32_CET_LEG_IW_EN 0x8
%define MSR_IA32_CET_NO_TRACK_EN 0x10
%define MSR_IA32_CET_SUPPRESS_DIS 0x20
%define MSR_IA32_CET_SUPPRESS 0x400
%define MSR_IA32_CET_TRACKER 0x800
%define MSR_IA32_PL0_SSP 0x6A4
%define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR 0x6A8
%define CR4_CET 0x800000
%define MSR_IA32_MISC_ENABLE 0x1A0 %define MSR_IA32_MISC_ENABLE 0x1A0
%define MSR_EFER 0xc0000080 %define MSR_EFER 0xc0000080
%define MSR_EFER_XD 0x800 %define MSR_EFER_XD 0x800