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https://github.com/acidanthera/audk.git
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MdeModulePkg AtaAtapiPassThru: Remove redundant functions
The functions that are never called have been removed. They are AhciCheckDeviceStatus,AhciPortReset,DRDYReady, DRDYReady2,WaitForBSYClear2 and AtaSoftReset. https://bugzilla.tianocore.org/show_bug.cgi?id=1062 v2: DRDYReady, DRDYReady2, WaitForBSYClear2 and AtaSoftReset are added to the commit message. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
shenglei
Star Zeng
parent
0629ae291a
commit
385fd1b846
@ -294,41 +294,6 @@ AhciCheckMemSet (
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}
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}
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}
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}
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/**
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Check if the device is still on port. It also checks if the AHCI controller
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supports the address and data count will be transferred.
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@param PciIo The PCI IO protocol instance.
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@param Port The number of port.
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@retval EFI_SUCCESS The device is attached to port and the transfer data is
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supported by AHCI controller.
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@retval EFI_UNSUPPORTED The transfer address and count is not supported by AHCI
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controller.
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@retval EFI_NOT_READY The physical communication between AHCI controller and device
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is not ready.
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**/
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EFI_STATUS
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EFIAPI
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AhciCheckDeviceStatus (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 Port
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)
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{
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UINT32 Data;
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UINT32 Offset;
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Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
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Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
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if (Data == EFI_AHCI_PORT_SSTS_DET_PCE) {
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return EFI_SUCCESS;
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}
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return EFI_NOT_READY;
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}
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/**
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/**
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@ -1361,75 +1326,6 @@ AhciStartCommand (
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return EFI_SUCCESS;
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return EFI_SUCCESS;
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}
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}
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/**
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Do AHCI port reset.
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@param PciIo The PCI IO protocol instance.
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@param Port The number of port.
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@param Timeout The timeout value of reset, uses 100ns as a unit.
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@retval EFI_DEVICE_ERROR The port reset unsuccessfully
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@retval EFI_TIMEOUT The reset operation is time out.
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@retval EFI_SUCCESS The port reset successfully.
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**/
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EFI_STATUS
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EFIAPI
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AhciPortReset (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN UINT8 Port,
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IN UINT64 Timeout
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)
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{
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EFI_STATUS Status;
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UINT32 Offset;
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AhciClearPortStatus (PciIo, Port);
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AhciStopCommand (PciIo, Port, Timeout);
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AhciDisableFisReceive (PciIo, Port, Timeout);
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AhciEnableFisReceive (PciIo, Port, Timeout);
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Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
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AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
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//
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// wait 5 millisecond before de-assert DET
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//
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MicroSecondDelay (5000);
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AhciAndReg (PciIo, Offset, (UINT32)EFI_AHCI_PORT_SCTL_MASK);
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//
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// wait 5 millisecond before de-assert DET
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//
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MicroSecondDelay (5000);
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//
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// Wait for communication to be re-established
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//
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Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
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Status = AhciWaitMmioSet (
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PciIo,
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Offset,
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EFI_AHCI_PORT_SSTS_DET_MASK,
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EFI_AHCI_PORT_SSTS_DET_PCE,
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Timeout
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "Port %d COMRESET failed: %r\n", Port, Status));
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return Status;
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}
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Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
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AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_ERR_CLEAR);
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return EFI_SUCCESS;
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}
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/**
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/**
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Do AHCI HBA reset.
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Do AHCI HBA reset.
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@ -627,146 +627,8 @@ DRQReady2 (
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return EFI_TIMEOUT;
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return EFI_TIMEOUT;
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}
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}
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/**
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This function is used to poll for the DRDY bit set in the Status Register. DRDY
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bit is set when the device is ready to accept command. Most ATA commands must be
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sent after DRDY set except the ATAPI Packet Command.
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@param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
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@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
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@param Timeout The time to complete the command, uses 100ns as a unit.
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@retval EFI_SUCCESS DRDY bit set within the time out.
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@retval EFI_TIMEOUT DRDY bit not set within the time out.
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@note Read Status Register will clear interrupt status.
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**/
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EFI_STATUS
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EFIAPI
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DRDYReady (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_IDE_REGISTERS *IdeRegisters,
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IN UINT64 Timeout
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)
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{
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UINT64 Delay;
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UINT8 StatusRegister;
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UINT8 ErrorRegister;
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BOOLEAN InfiniteWait;
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ASSERT (PciIo != NULL);
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ASSERT (IdeRegisters != NULL);
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if (Timeout == 0) {
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InfiniteWait = TRUE;
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} else {
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InfiniteWait = FALSE;
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}
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Delay = DivU64x32(Timeout, 1000) + 1;
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do {
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StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
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//
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// Wait for BSY == 0, then judge if DRDY is set or ERR is set
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//
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if ((StatusRegister & ATA_STSREG_BSY) == 0) {
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if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
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ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
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if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
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return EFI_ABORTED;
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}
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return EFI_DEVICE_ERROR;
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}
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if ((StatusRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {
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return EFI_SUCCESS;
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} else {
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return EFI_DEVICE_ERROR;
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}
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}
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//
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// Stall for 100 microseconds.
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//
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MicroSecondDelay (100);
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Delay--;
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} while (InfiniteWait || (Delay > 0));
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return EFI_TIMEOUT;
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}
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/**
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This function is used to poll for the DRDY bit set in the Alternate Status Register.
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DRDY bit is set when the device is ready to accept command. Most ATA commands must
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be sent after DRDY set except the ATAPI Packet Command.
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@param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
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@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
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@param Timeout The time to complete the command, uses 100ns as a unit.
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@retval EFI_SUCCESS DRDY bit set within the time out.
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@retval EFI_TIMEOUT DRDY bit not set within the time out.
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@note Read Alternate Status Register will clear interrupt status.
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**/
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EFI_STATUS
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EFIAPI
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DRDYReady2 (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_IDE_REGISTERS *IdeRegisters,
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IN UINT64 Timeout
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)
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{
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UINT64 Delay;
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UINT8 AltRegister;
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UINT8 ErrorRegister;
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BOOLEAN InfiniteWait;
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ASSERT (PciIo != NULL);
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ASSERT (IdeRegisters != NULL);
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if (Timeout == 0) {
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InfiniteWait = TRUE;
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} else {
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InfiniteWait = FALSE;
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}
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Delay = DivU64x32(Timeout, 1000) + 1;
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do {
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AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
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//
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// Wait for BSY == 0, then judge if DRDY is set or ERR is set
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//
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if ((AltRegister & ATA_STSREG_BSY) == 0) {
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if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
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ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
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if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
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return EFI_ABORTED;
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}
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return EFI_DEVICE_ERROR;
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}
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if ((AltRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {
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return EFI_SUCCESS;
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} else {
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return EFI_DEVICE_ERROR;
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}
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}
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//
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// Stall for 100 microseconds.
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//
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MicroSecondDelay (100);
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Delay--;
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} while (InfiniteWait || (Delay > 0));
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return EFI_TIMEOUT;
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}
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/**
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/**
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This function is used to poll for the BSY bit clear in the Status Register. BSY
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This function is used to poll for the BSY bit clear in the Status Register. BSY
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@ -822,59 +684,6 @@ WaitForBSYClear (
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return EFI_TIMEOUT;
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return EFI_TIMEOUT;
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}
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}
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/**
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This function is used to poll for the BSY bit clear in the Status Register. BSY
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is clear when the device is not busy. Every command must be sent after device is not busy.
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@param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
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@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
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@param Timeout The time to complete the command, uses 100ns as a unit.
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@retval EFI_SUCCESS BSY bit clear within the time out.
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@retval EFI_TIMEOUT BSY bit not clear within the time out.
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@note Read Status Register will clear interrupt status.
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**/
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EFI_STATUS
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EFIAPI
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WaitForBSYClear2 (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_IDE_REGISTERS *IdeRegisters,
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IN UINT64 Timeout
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)
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{
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UINT64 Delay;
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UINT8 AltStatusRegister;
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BOOLEAN InfiniteWait;
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ASSERT (PciIo != NULL);
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ASSERT (IdeRegisters != NULL);
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if (Timeout == 0) {
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InfiniteWait = TRUE;
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} else {
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InfiniteWait = FALSE;
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}
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Delay = DivU64x32(Timeout, 1000) + 1;
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do {
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AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
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if ((AltStatusRegister & ATA_STSREG_BSY) == 0x00) {
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return EFI_SUCCESS;
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}
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//
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// Stall for 100 microseconds.
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//
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MicroSecondDelay (100);
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Delay--;
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} while (InfiniteWait || (Delay > 0));
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return EFI_TIMEOUT;
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}
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/**
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/**
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Get IDE i/o port registers' base addresses by mode.
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Get IDE i/o port registers' base addresses by mode.
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@ -1017,72 +826,6 @@ GetIdeRegisterIoAddr (
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return EFI_SUCCESS;
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return EFI_SUCCESS;
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}
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}
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/**
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This function is used to implement the Soft Reset on the specified device. But,
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the ATA Soft Reset mechanism is so strong a reset method that it will force
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resetting on both devices connected to the same cable.
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It is called by IdeBlkIoReset(), a interface function of Block
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I/O protocol.
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This function can also be used by the ATAPI device to perform reset when
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ATAPI Reset command is failed.
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@param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
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@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
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@param Timeout The time to complete the command, uses 100ns as a unit.
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@retval EFI_SUCCESS Soft reset completes successfully.
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@retval EFI_DEVICE_ERROR Any step during the reset process is failed.
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@note The registers initial values after ATA soft reset are different
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to the ATA device and ATAPI device.
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**/
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EFI_STATUS
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EFIAPI
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AtaSoftReset (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_IDE_REGISTERS *IdeRegisters,
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IN UINT64 Timeout
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)
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{
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UINT8 DeviceControl;
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DeviceControl = 0;
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//
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// disable Interrupt and set SRST bit to initiate soft reset
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//
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DeviceControl = ATA_CTLREG_SRST | ATA_CTLREG_IEN_L;
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IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
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//
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// SRST should assert for at least 5 us, we use 10 us for
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// better compatibility
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//
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MicroSecondDelay (10);
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//
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// Enable interrupt to support UDMA, and clear SRST bit
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//
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DeviceControl = 0;
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IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
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//
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// Wait for at least 10 ms to check BSY status, we use 10 ms
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// for better compatibility
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//
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MicroSecondDelay (10000);
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//
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// slave device needs at most 31ms to clear BSY
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//
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if (WaitForBSYClear (PciIo, IdeRegisters, Timeout) == EFI_TIMEOUT) {
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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/**
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/**
|
||||||
Send ATA Ext command into device with NON_DATA protocol.
|
Send ATA Ext command into device with NON_DATA protocol.
|
||||||
|
|||||||
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Reference in New Issue
Block a user