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Fix >4G issue on IDT not restored correctly. 

Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address.
If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR here.
Interrupt is already disabled here, so it is safety to update IDTR.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
Reviewed-by: "Yarlagadda, Satya P" <satya.p.yarlagadda@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19246 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Yao, Jiewen 2015-12-15 04:27:00 +00:00 committed by jyao1
parent fb567b2f74
commit 3b567f08f9
1 changed files with 13 additions and 1 deletions
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14
IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c
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@ -89,6 +89,18 @@ Execute32BitCode (
IN UINT64 Param1
)
{
return AsmExecute32BitCode (Function, Param1, 0, &mGdt);
EFI_STATUS Status;
IA32_DESCRIPTOR Idtr;
//
// Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address.
// If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR here for X64 only.
// Interrupt is already disabled here, so it is safety to update IDTR.
//
AsmReadIdtr (&Idtr);
Status = AsmExecute32BitCode (Function, Param1, 0, &mGdt);
AsmWriteIdtr (&Idtr);
return Status;
}