mirror of https://github.com/acidanthera/audk.git
OvmfPkg: Introduce XenPlatformPei
Introduce XenPlatformPei, a copy of OvmfPkg/PlatformPei without some
of QEMU specific initialization, Xen does not support QemuFwCfg.
This new module will be adjusted to accommodate Xen PVH.
fw_cfg dependents that have been removed, which are dynamically skipped
when running PlatformPei on Xen:
- GetFirstNonAddress(): controlling the 64-bit PCI MMIO aperture via the
(experimental) "opt/ovmf/X-PciMmio64Mb" file
- GetFirstNonAddress(): honoring the hotplug DIMM area
("etc/reserved-memory-end") in the placement of the 64-bit PCI MMIO
aperture
- NoexecDxeInitialization() is removed, so PcdPropertiesTableEnable and
PcdSetNxForStack are left constant FALSE (not set dynamically from
fw_cfg "opt/ovmf/PcdXxxx")
- MaxCpuCountInitialization(), PublishPeiMemory(): the max CPU count is
not taken from the QemuFwCfgItemSmpCpuCount fw_cfg key;
PcdCpuMaxLogicalProcessorNumber is used intact and
PcdCpuApInitTimeOutInMicroSeconds is never changed or used.
- InitializeXenPlatform(), S3Verification(): S3 is assumed disabled (not
consulting "etc/system-states" via QemuFwCfgS3Enabled()).
- InstallFeatureControlCallback(): the feature control MSR is not set
from "etc/msr_feature_control"
(also removed FeatureControl.c as there is nothing been executed)
Also removed:
- SMRAM/TSEG-related low mem size adjusting (PcdSmmSmramRequire is
assumed FALSE) in PublishPeiMemory(),
- QemuInitializeRam() entirely,
Xen related changes:
- Have removed the module variable mXen, as it should be always true.
- Have the platform PEI initialization fails if Xen has not been
detected.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20190813113119.14804-5-anthony.perard@citrix.com>
This commit is contained in:
Anthony PERARD
Laszlo Ersek
parent
c05de360ec
commit
3b96221f77
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@ -379,6 +379,7 @@ F: OvmfPkg/PlatformPei/Xen.*
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F: OvmfPkg/SmbiosPlatformDxe/*Xen.c
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F: OvmfPkg/XenBusDxe/
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F: OvmfPkg/XenIoPciDxe/
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F: OvmfPkg/XenPlatformPei/
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F: OvmfPkg/XenPvBlkDxe/
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F: OvmfPkg/XenResetVector/
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R: Anthony Perard <anthony.perard@citrix.com>
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@ -523,7 +523,7 @@
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}
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MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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OvmfPkg/PlatformPei/PlatformPei.inf
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OvmfPkg/XenPlatformPei/XenPlatformPei.inf
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UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
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UefiCpuPkg/CpuMpPei/CpuMpPei.inf
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@ -152,7 +152,7 @@ INF MdeModulePkg/Core/Pei/PeiMain.inf
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INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
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INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
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INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
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INF OvmfPkg/PlatformPei/PlatformPei.inf
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INF OvmfPkg/XenPlatformPei/XenPlatformPei.inf
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INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
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INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
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@ -0,0 +1,64 @@
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/**@file
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Initialize Secure Encrypted Virtualization (SEV) support
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Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
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Copyright (c) 2019, Citrix Systems, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <Library/DebugLib.h>
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#include <Library/MemEncryptSevLib.h>
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#include <Library/PcdLib.h>
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#include <PiPei.h>
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#include <Register/Amd/Cpuid.h>
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#include <Register/Cpuid.h>
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#include "Platform.h"
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/**
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Function checks if SEV support is available, if present then it sets
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the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption mask.
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**/
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VOID
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AmdSevInitialize (
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VOID
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)
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{
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CPUID_MEMORY_ENCRYPTION_INFO_EBX Ebx;
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UINT64 EncryptionMask;
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RETURN_STATUS PcdStatus;
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//
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// Check if SEV is enabled
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//
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if (!MemEncryptSevIsEnabled ()) {
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return;
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}
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//
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// CPUID Fn8000_001F[EBX] Bit 0:5 (memory encryption bit position)
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//
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AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, NULL, &Ebx.Uint32, NULL, NULL);
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EncryptionMask = LShiftU64 (1, Ebx.Bits.PtePosBits);
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//
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// Set Memory Encryption Mask PCD
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//
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PcdStatus = PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, EncryptionMask);
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ASSERT_RETURN_ERROR (PcdStatus);
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DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask));
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//
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// Set Pcd to Deny the execution of option ROM when security
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// violation.
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//
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PcdStatus = PcdSet32S (PcdOptionRomImageVerificationPolicy, 0x4);
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ASSERT_RETURN_ERROR (PcdStatus);
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}
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@ -0,0 +1,112 @@
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/**@file
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Install a callback to clear cache on all processors.
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This is for conformance with the TCG "Platform Reset Attack Mitigation
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Specification". Because clearing the CPU caches at boot doesn't impact
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performance significantly, do it unconditionally, for simplicity's
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sake.
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Copyright (C) 2018, Red Hat, Inc.
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Copyright (c) 2019, Citrix Systems, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Ppi/MpServices.h>
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#include "Platform.h"
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/**
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Invalidate data & instruction caches.
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All APs execute this function in parallel. The BSP executes the function
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separately.
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@param[in,out] WorkSpace Pointer to the input/output argument workspace
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shared by all processors.
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**/
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STATIC
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VOID
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EFIAPI
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ClearCache (
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IN OUT VOID *WorkSpace
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)
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{
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WriteBackInvalidateDataCache ();
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InvalidateInstructionCache ();
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}
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/**
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Notification function called when EFI_PEI_MP_SERVICES_PPI becomes available.
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@param[in] PeiServices Indirect reference to the PEI Services Table.
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@param[in] NotifyDescriptor Address of the notification descriptor data
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structure.
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@param[in] Ppi Address of the PPI that was installed.
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@return Status of the notification. The status code returned from this
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function is ignored.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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ClearCacheOnMpServicesAvailable (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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)
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{
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EFI_PEI_MP_SERVICES_PPI *MpServices;
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "%a: %a\n", gEfiCallerBaseName, __FUNCTION__));
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//
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// Clear cache on all the APs in parallel.
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//
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MpServices = Ppi;
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Status = MpServices->StartupAllAPs (
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(CONST EFI_PEI_SERVICES **)PeiServices,
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MpServices,
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ClearCache, // Procedure
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FALSE, // SingleThread
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0, // TimeoutInMicroSeconds: inf.
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NULL // ProcedureArgument
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);
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if (EFI_ERROR (Status) && Status != EFI_NOT_STARTED) {
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DEBUG ((DEBUG_ERROR, "%a: StartupAllAps(): %r\n", __FUNCTION__, Status));
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return Status;
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}
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//
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// Now clear cache on the BSP too.
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//
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ClearCache (NULL);
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return EFI_SUCCESS;
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}
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//
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// Notification object for registering the callback, for when
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// EFI_PEI_MP_SERVICES_PPI becomes available.
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//
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STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mMpServicesNotify = {
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EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | // Flags
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EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiMpServicesPpiGuid, // Guid
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ClearCacheOnMpServicesAvailable // Notify
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};
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VOID
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InstallClearCacheCallback (
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VOID
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)
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{
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EFI_STATUS Status;
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Status = PeiServicesNotifyPpi (&mMpServicesNotify);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: failed to set up MP Services callback: %r\n",
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__FUNCTION__, Status));
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}
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}
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@ -0,0 +1,60 @@
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/** @file
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PC/AT CMOS access routines
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Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2019, Citrix Systems, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Cmos.h"
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#include "Library/IoLib.h"
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/**
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Reads 8-bits of CMOS data.
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Reads the 8-bits of CMOS data at the location specified by Index.
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The 8-bit read value is returned.
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@param Index The CMOS location to read.
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@return The value read.
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**/
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UINT8
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EFIAPI
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CmosRead8 (
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IN UINTN Index
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)
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{
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IoWrite8 (0x70, (UINT8) Index);
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return IoRead8 (0x71);
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}
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/**
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Writes 8-bits of CMOS data.
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Writes 8-bits of CMOS data to the location specified by Index
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with the value specified by Value and returns Value.
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@param Index The CMOS location to write.
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@param Value The value to write to CMOS.
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@return The value written to CMOS.
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**/
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UINT8
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EFIAPI
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CmosWrite8 (
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IN UINTN Index,
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IN UINT8 Value
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)
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{
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IoWrite8 (0x70, (UINT8) Index);
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IoWrite8 (0x71, Value);
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return Value;
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}
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@ -0,0 +1,52 @@
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/** @file
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PC/AT CMOS access routines
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Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2019, Citrix Systems, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __CMOS_H__
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#define __CMOS_H__
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/**
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Reads 8-bits of CMOS data.
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Reads the 8-bits of CMOS data at the location specified by Index.
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The 8-bit read value is returned.
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@param Index The CMOS location to read.
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@return The value read.
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**/
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UINT8
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EFIAPI
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CmosRead8 (
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IN UINTN Index
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);
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/**
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Writes 8-bits of CMOS data.
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Writes 8-bits of CMOS data to the location specified by Index
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with the value specified by Value and returns Value.
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@param Index The CMOS location to write.
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@param Value The value to write to CMOS.
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@return The value written to CMOS.
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**/
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UINT8
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EFIAPI
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CmosWrite8 (
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IN UINTN Index,
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IN UINT8 Value
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);
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#endif
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@ -0,0 +1,76 @@
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/** @file
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Build FV related hobs for platform.
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Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2019, Citrix Systems, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PiPei.h"
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#include "Platform.h"
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PcdLib.h>
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/**
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Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
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and DXE know about them.
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@retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
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||||
**/
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EFI_STATUS
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PeiFvInitialization (
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VOID
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||||
)
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||||
{
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DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
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||||
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//
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// Create a memory allocation HOB for the PEI FV.
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//
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||||
// Allocate as ACPI NVS is S3 is supported
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//
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||||
BuildMemoryAllocationHob (
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PcdGet32 (PcdOvmfPeiMemFvBase),
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PcdGet32 (PcdOvmfPeiMemFvSize),
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||||
EfiBootServicesData
|
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);
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||||
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||||
//
|
||||
// Let DXE know about the DXE FV
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||||
//
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||||
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
|
||||
|
||||
//
|
||||
// Create a memory allocation HOB for the DXE FV.
|
||||
//
|
||||
// If "secure" S3 is needed, then SEC will decompress both PEI and DXE
|
||||
// firmware volumes at S3 resume too, hence we need to keep away the OS from
|
||||
// DXEFV as well. Otherwise we only need to keep away DXE itself from the
|
||||
// DXEFV area.
|
||||
//
|
||||
BuildMemoryAllocationHob (
|
||||
PcdGet32 (PcdOvmfDxeMemFvBase),
|
||||
PcdGet32 (PcdOvmfDxeMemFvSize),
|
||||
EfiBootServicesData
|
||||
);
|
||||
|
||||
//
|
||||
// Let PEI know about the DXE FV so it can find the DXE Core
|
||||
//
|
||||
PeiServicesInstallFvInfoPpi (
|
||||
NULL,
|
||||
(VOID *)(UINTN) PcdGet32 (PcdOvmfDxeMemFvBase),
|
||||
PcdGet32 (PcdOvmfDxeMemFvSize),
|
||||
NULL,
|
||||
NULL
|
||||
);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,421 @@
|
|||
/**@file
|
||||
Memory Detection for Virtual Machines.
|
||||
|
||||
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2019, Citrix Systems, Inc.
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
Module Name:
|
||||
|
||||
MemDetect.c
|
||||
|
||||
**/
|
||||
|
||||
//
|
||||
// The package level header files this module uses
|
||||
//
|
||||
#include <IndustryStandard/Q35MchIch9.h>
|
||||
#include <PiPei.h>
|
||||
|
||||
//
|
||||
// The Library classes this module consumes
|
||||
//
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/HobLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/PciLib.h>
|
||||
#include <Library/PeimEntryPoint.h>
|
||||
#include <Library/ResourcePublicationLib.h>
|
||||
|
||||
#include "Platform.h"
|
||||
#include "Cmos.h"
|
||||
|
||||
UINT8 mPhysMemAddressWidth;
|
||||
|
||||
STATIC UINT32 mS3AcpiReservedMemoryBase;
|
||||
STATIC UINT32 mS3AcpiReservedMemorySize;
|
||||
|
||||
STATIC UINT16 mQ35TsegMbytes;
|
||||
|
||||
VOID
|
||||
Q35TsegMbytesInitialization (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT16 ExtendedTsegMbytes;
|
||||
RETURN_STATUS PcdStatus;
|
||||
|
||||
if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
|
||||
DEBUG ((
|
||||
DEBUG_ERROR,
|
||||
"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
|
||||
"only DID=0x%04x (Q35) is supported\n",
|
||||
__FUNCTION__,
|
||||
mHostBridgeDevId,
|
||||
INTEL_Q35_MCH_DEVICE_ID
|
||||
));
|
||||
ASSERT (FALSE);
|
||||
CpuDeadLoop ();
|
||||
}
|
||||
|
||||
//
|
||||
// Check if QEMU offers an extended TSEG.
|
||||
//
|
||||
// This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
|
||||
// register, and reading back the register.
|
||||
//
|
||||
// On a QEMU machine type that does not offer an extended TSEG, the initial
|
||||
// write overwrites whatever value a malicious guest OS may have placed in
|
||||
// the (unimplemented) register, before entering S3 or rebooting.
|
||||
// Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
|
||||
//
|
||||
// On a QEMU machine type that offers an extended TSEG, the initial write
|
||||
// triggers an update to the register. Subsequently, the value read back
|
||||
// (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
|
||||
// number of megabytes.
|
||||
//
|
||||
PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
|
||||
ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
|
||||
if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
|
||||
mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
|
||||
return;
|
||||
}
|
||||
|
||||
DEBUG ((
|
||||
DEBUG_INFO,
|
||||
"%a: QEMU offers an extended TSEG (%d MB)\n",
|
||||
__FUNCTION__,
|
||||
ExtendedTsegMbytes
|
||||
));
|
||||
PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
mQ35TsegMbytes = ExtendedTsegMbytes;
|
||||
}
|
||||
|
||||
|
||||
UINT32
|
||||
GetSystemMemorySizeBelow4gb (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT8 Cmos0x34;
|
||||
UINT8 Cmos0x35;
|
||||
|
||||
//
|
||||
// CMOS 0x34/0x35 specifies the system memory above 16 MB.
|
||||
// * CMOS(0x35) is the high byte
|
||||
// * CMOS(0x34) is the low byte
|
||||
// * The size is specified in 64kb chunks
|
||||
// * Since this is memory above 16MB, the 16MB must be added
|
||||
// into the calculation to get the total memory size.
|
||||
//
|
||||
|
||||
Cmos0x34 = (UINT8) CmosRead8 (0x34);
|
||||
Cmos0x35 = (UINT8) CmosRead8 (0x35);
|
||||
|
||||
return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
|
||||
}
|
||||
|
||||
|
||||
STATIC
|
||||
UINT64
|
||||
GetSystemMemorySizeAbove4gb (
|
||||
)
|
||||
{
|
||||
UINT32 Size;
|
||||
UINTN CmosIndex;
|
||||
|
||||
//
|
||||
// CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
|
||||
// * CMOS(0x5d) is the most significant size byte
|
||||
// * CMOS(0x5c) is the middle size byte
|
||||
// * CMOS(0x5b) is the least significant size byte
|
||||
// * The size is specified in 64kb chunks
|
||||
//
|
||||
|
||||
Size = 0;
|
||||
for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
|
||||
Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
|
||||
}
|
||||
|
||||
return LShiftU64 (Size, 16);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Return the highest address that DXE could possibly use, plus one.
|
||||
**/
|
||||
STATIC
|
||||
UINT64
|
||||
GetFirstNonAddress (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 FirstNonAddress;
|
||||
UINT64 Pci64Base, Pci64Size;
|
||||
RETURN_STATUS PcdStatus;
|
||||
|
||||
FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();
|
||||
|
||||
//
|
||||
// If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
|
||||
// resources to 32-bit anyway. See DegradeResource() in
|
||||
// "PciResourceSupport.c".
|
||||
//
|
||||
#ifdef MDE_CPU_IA32
|
||||
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
|
||||
return FirstNonAddress;
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// Otherwise, in order to calculate the highest address plus one, we must
|
||||
// consider the 64-bit PCI host aperture too. Fetch the default size.
|
||||
//
|
||||
Pci64Size = PcdGet64 (PcdPciMmio64Size);
|
||||
|
||||
if (Pci64Size == 0) {
|
||||
if (mBootMode != BOOT_ON_S3_RESUME) {
|
||||
DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",
|
||||
__FUNCTION__));
|
||||
PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
}
|
||||
|
||||
//
|
||||
// There's nothing more to do; the amount of memory above 4GB fully
|
||||
// determines the highest address plus one. The memory hotplug area (see
|
||||
// below) plays no role for the firmware in this case.
|
||||
//
|
||||
return FirstNonAddress;
|
||||
}
|
||||
|
||||
//
|
||||
// SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
|
||||
// that the host can map it with 1GB hugepages. Follow suit.
|
||||
//
|
||||
Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
|
||||
Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);
|
||||
|
||||
//
|
||||
// The 64-bit PCI host aperture should also be "naturally" aligned. The
|
||||
// alignment is determined by rounding the size of the aperture down to the
|
||||
// next smaller or equal power of two. That is, align the aperture by the
|
||||
// largest BAR size that can fit into it.
|
||||
//
|
||||
Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));
|
||||
|
||||
if (mBootMode != BOOT_ON_S3_RESUME) {
|
||||
//
|
||||
// The core PciHostBridgeDxe driver will automatically add this range to
|
||||
// the GCD memory space map through our PciHostBridgeLib instance; here we
|
||||
// only need to set the PCDs.
|
||||
//
|
||||
PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
|
||||
DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
|
||||
__FUNCTION__, Pci64Base, Pci64Size));
|
||||
}
|
||||
|
||||
//
|
||||
// The useful address space ends with the 64-bit PCI host aperture.
|
||||
//
|
||||
FirstNonAddress = Pci64Base + Pci64Size;
|
||||
return FirstNonAddress;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
|
||||
**/
|
||||
VOID
|
||||
AddressWidthInitialization (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 FirstNonAddress;
|
||||
|
||||
//
|
||||
// As guest-physical memory size grows, the permanent PEI RAM requirements
|
||||
// are dominated by the identity-mapping page tables built by the DXE IPL.
|
||||
// The DXL IPL keys off of the physical address bits advertized in the CPU
|
||||
// HOB. To conserve memory, we calculate the minimum address width here.
|
||||
//
|
||||
FirstNonAddress = GetFirstNonAddress ();
|
||||
mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
|
||||
|
||||
//
|
||||
// If FirstNonAddress is not an integral power of two, then we need an
|
||||
// additional bit.
|
||||
//
|
||||
if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
|
||||
++mPhysMemAddressWidth;
|
||||
}
|
||||
|
||||
//
|
||||
// The minimum address width is 36 (covers up to and excluding 64 GB, which
|
||||
// is the maximum for Ia32 + PAE). The theoretical architecture maximum for
|
||||
// X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
|
||||
// can simply assert that here, since 48 bits are good enough for 256 TB.
|
||||
//
|
||||
if (mPhysMemAddressWidth <= 36) {
|
||||
mPhysMemAddressWidth = 36;
|
||||
}
|
||||
ASSERT (mPhysMemAddressWidth <= 48);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Calculate the cap for the permanent PEI memory.
|
||||
**/
|
||||
STATIC
|
||||
UINT32
|
||||
GetPeiMemoryCap (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
BOOLEAN Page1GSupport;
|
||||
UINT32 RegEax;
|
||||
UINT32 RegEdx;
|
||||
UINT32 Pml4Entries;
|
||||
UINT32 PdpEntries;
|
||||
UINTN TotalPages;
|
||||
|
||||
//
|
||||
// If DXE is 32-bit, then just return the traditional 64 MB cap.
|
||||
//
|
||||
#ifdef MDE_CPU_IA32
|
||||
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
|
||||
return SIZE_64MB;
|
||||
}
|
||||
#endif
|
||||
|
||||
//
|
||||
// Dependent on physical address width, PEI memory allocations can be
|
||||
// dominated by the page tables built for 64-bit DXE. So we key the cap off
|
||||
// of those. The code below is based on CreateIdentityMappingPageTables() in
|
||||
// "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
|
||||
//
|
||||
Page1GSupport = FALSE;
|
||||
if (PcdGetBool (PcdUse1GPageTable)) {
|
||||
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
|
||||
if (RegEax >= 0x80000001) {
|
||||
AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
|
||||
if ((RegEdx & BIT26) != 0) {
|
||||
Page1GSupport = TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mPhysMemAddressWidth <= 39) {
|
||||
Pml4Entries = 1;
|
||||
PdpEntries = 1 << (mPhysMemAddressWidth - 30);
|
||||
ASSERT (PdpEntries <= 0x200);
|
||||
} else {
|
||||
Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
|
||||
ASSERT (Pml4Entries <= 0x200);
|
||||
PdpEntries = 512;
|
||||
}
|
||||
|
||||
TotalPages = Page1GSupport ? Pml4Entries + 1 :
|
||||
(PdpEntries + 1) * Pml4Entries + 1;
|
||||
ASSERT (TotalPages <= 0x40201);
|
||||
|
||||
//
|
||||
// Add 64 MB for miscellaneous allocations. Note that for
|
||||
// mPhysMemAddressWidth values close to 36, the cap will actually be
|
||||
// dominated by this increment.
|
||||
//
|
||||
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Publish PEI core memory
|
||||
|
||||
@return EFI_SUCCESS The PEIM initialized successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
PublishPeiMemory (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase;
|
||||
UINT64 MemorySize;
|
||||
UINT32 LowerMemorySize;
|
||||
UINT32 PeiMemoryCap;
|
||||
|
||||
LowerMemorySize = GetSystemMemorySizeBelow4gb ();
|
||||
|
||||
if (mBootMode == BOOT_ON_S3_RESUME) {
|
||||
MemoryBase = mS3AcpiReservedMemoryBase;
|
||||
MemorySize = mS3AcpiReservedMemorySize;
|
||||
} else {
|
||||
PeiMemoryCap = GetPeiMemoryCap ();
|
||||
DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
|
||||
__FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
|
||||
|
||||
//
|
||||
// Determine the range of memory to use during PEI
|
||||
//
|
||||
MemoryBase =
|
||||
PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
|
||||
MemorySize = LowerMemorySize - MemoryBase;
|
||||
if (MemorySize > PeiMemoryCap) {
|
||||
MemoryBase = LowerMemorySize - PeiMemoryCap;
|
||||
MemorySize = PeiMemoryCap;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Publish this memory to the PEI Core
|
||||
//
|
||||
Status = PublishSystemMemory(MemoryBase, MemorySize);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Publish system RAM and reserve memory regions
|
||||
|
||||
**/
|
||||
VOID
|
||||
InitializeRamRegions (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
XenPublishRamRegions ();
|
||||
|
||||
if (mBootMode != BOOT_ON_S3_RESUME) {
|
||||
//
|
||||
// Reserve the lock box storage area
|
||||
//
|
||||
// Since this memory range will be used on S3 resume, it must be
|
||||
// reserved as ACPI NVS.
|
||||
//
|
||||
// If S3 is unsupported, then various drivers might still write to the
|
||||
// LockBox area. We ought to prevent DXE from serving allocation requests
|
||||
// such that they would overlap the LockBox storage.
|
||||
//
|
||||
ZeroMem (
|
||||
(VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
|
||||
(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
|
||||
);
|
||||
BuildMemoryAllocationHob (
|
||||
(EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
|
||||
(UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
|
||||
EfiBootServicesData
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,444 @@
|
|||
/**@file
|
||||
Platform PEI driver
|
||||
|
||||
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
|
||||
Copyright (c) 2019, Citrix Systems, Inc.
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
//
|
||||
// The package level header files this module uses
|
||||
//
|
||||
#include <PiPei.h>
|
||||
|
||||
//
|
||||
// The Library classes this module consumes
|
||||
//
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/HobLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/PciLib.h>
|
||||
#include <Library/PeimEntryPoint.h>
|
||||
#include <Library/PeiServicesLib.h>
|
||||
#include <Library/ResourcePublicationLib.h>
|
||||
#include <Guid/MemoryTypeInformation.h>
|
||||
#include <Ppi/MasterBootMode.h>
|
||||
#include <IndustryStandard/Pci22.h>
|
||||
#include <OvmfPlatforms.h>
|
||||
|
||||
#include "Platform.h"
|
||||
#include "Cmos.h"
|
||||
|
||||
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
|
||||
{ EfiACPIMemoryNVS, 0x004 },
|
||||
{ EfiACPIReclaimMemory, 0x008 },
|
||||
{ EfiReservedMemoryType, 0x004 },
|
||||
{ EfiRuntimeServicesData, 0x024 },
|
||||
{ EfiRuntimeServicesCode, 0x030 },
|
||||
{ EfiBootServicesCode, 0x180 },
|
||||
{ EfiBootServicesData, 0xF00 },
|
||||
{ EfiMaxMemoryType, 0x000 }
|
||||
};
|
||||
|
||||
|
||||
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
|
||||
{
|
||||
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
|
||||
&gEfiPeiMasterBootModePpiGuid,
|
||||
NULL
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
UINT16 mHostBridgeDevId;
|
||||
|
||||
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
|
||||
|
||||
|
||||
VOID
|
||||
AddIoMemoryBaseSizeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
UINT64 MemorySize
|
||||
)
|
||||
{
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_MAPPED_IO,
|
||||
EFI_RESOURCE_ATTRIBUTE_PRESENT |
|
||||
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
|
||||
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_TESTED,
|
||||
MemoryBase,
|
||||
MemorySize
|
||||
);
|
||||
}
|
||||
|
||||
VOID
|
||||
AddReservedMemoryBaseSizeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
UINT64 MemorySize,
|
||||
BOOLEAN Cacheable
|
||||
)
|
||||
{
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_MEMORY_RESERVED,
|
||||
EFI_RESOURCE_ATTRIBUTE_PRESENT |
|
||||
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
|
||||
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
|
||||
(Cacheable ?
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
|
||||
0
|
||||
) |
|
||||
EFI_RESOURCE_ATTRIBUTE_TESTED,
|
||||
MemoryBase,
|
||||
MemorySize
|
||||
);
|
||||
}
|
||||
|
||||
VOID
|
||||
AddIoMemoryRangeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
EFI_PHYSICAL_ADDRESS MemoryLimit
|
||||
)
|
||||
{
|
||||
AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
AddMemoryBaseSizeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
UINT64 MemorySize
|
||||
)
|
||||
{
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_SYSTEM_MEMORY,
|
||||
EFI_RESOURCE_ATTRIBUTE_PRESENT |
|
||||
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
|
||||
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_TESTED,
|
||||
MemoryBase,
|
||||
MemorySize
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
AddMemoryRangeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
EFI_PHYSICAL_ADDRESS MemoryLimit
|
||||
)
|
||||
{
|
||||
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
MemMapInitialization (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 PciIoBase;
|
||||
UINT64 PciIoSize;
|
||||
RETURN_STATUS PcdStatus;
|
||||
|
||||
PciIoBase = 0xC000;
|
||||
PciIoSize = 0x4000;
|
||||
|
||||
//
|
||||
// Create Memory Type Information HOB
|
||||
//
|
||||
BuildGuidDataHob (
|
||||
&gEfiMemoryTypeInformationGuid,
|
||||
mDefaultMemoryTypeInformation,
|
||||
sizeof(mDefaultMemoryTypeInformation)
|
||||
);
|
||||
|
||||
//
|
||||
// Video memory + Legacy BIOS region
|
||||
//
|
||||
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
|
||||
|
||||
//
|
||||
// Add PCI IO Port space available for PCI resource allocations.
|
||||
//
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_IO,
|
||||
EFI_RESOURCE_ATTRIBUTE_PRESENT |
|
||||
EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
|
||||
PciIoBase,
|
||||
PciIoSize
|
||||
);
|
||||
PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
}
|
||||
|
||||
VOID
|
||||
PciExBarInitialization (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
union {
|
||||
UINT64 Uint64;
|
||||
UINT32 Uint32[2];
|
||||
} PciExBarBase;
|
||||
|
||||
//
|
||||
// We only support the 256MB size for the MMCONFIG area:
|
||||
// 256 buses * 32 devices * 8 functions * 4096 bytes config space.
|
||||
//
|
||||
// The masks used below enforce the Q35 requirements that the MMCONFIG area
|
||||
// be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
|
||||
//
|
||||
// Note that (b) also ensures that the minimum address width we have
|
||||
// determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
|
||||
// for DXE's page tables to cover the MMCONFIG area.
|
||||
//
|
||||
PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
|
||||
ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
|
||||
ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
|
||||
|
||||
//
|
||||
// Clear the PCIEXBAREN bit first, before programming the high register.
|
||||
//
|
||||
PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
|
||||
|
||||
//
|
||||
// Program the high register. Then program the low register, setting the
|
||||
// MMCONFIG area size and enabling decoding at once.
|
||||
//
|
||||
PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
|
||||
PciWrite32 (
|
||||
DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
|
||||
PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
|
||||
);
|
||||
}
|
||||
|
||||
VOID
|
||||
MiscInitialization (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN PmCmd;
|
||||
UINTN Pmba;
|
||||
UINT32 PmbaAndVal;
|
||||
UINT32 PmbaOrVal;
|
||||
UINTN AcpiCtlReg;
|
||||
UINT8 AcpiEnBit;
|
||||
RETURN_STATUS PcdStatus;
|
||||
|
||||
//
|
||||
// Disable A20 Mask
|
||||
//
|
||||
IoOr8 (0x92, BIT1);
|
||||
|
||||
//
|
||||
// Build the CPU HOB with guest RAM size dependent address width and 16-bits
|
||||
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
|
||||
// S3 resume as well, so we build it unconditionally.)
|
||||
//
|
||||
BuildCpuHob (mPhysMemAddressWidth, 16);
|
||||
|
||||
//
|
||||
// Determine platform type and save Host Bridge DID to PCD
|
||||
//
|
||||
switch (mHostBridgeDevId) {
|
||||
case INTEL_82441_DEVICE_ID:
|
||||
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
|
||||
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
|
||||
PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
|
||||
PmbaOrVal = PIIX4_PMBA_VALUE;
|
||||
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
|
||||
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
|
||||
break;
|
||||
case INTEL_Q35_MCH_DEVICE_ID:
|
||||
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
|
||||
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
|
||||
PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
|
||||
PmbaOrVal = ICH9_PMBASE_VALUE;
|
||||
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
|
||||
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
|
||||
break;
|
||||
default:
|
||||
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
|
||||
__FUNCTION__, mHostBridgeDevId));
|
||||
ASSERT (FALSE);
|
||||
return;
|
||||
}
|
||||
PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
|
||||
//
|
||||
// If the appropriate IOspace enable bit is set, assume the ACPI PMBA
|
||||
// has been configured (e.g., by Xen) and skip the setup here.
|
||||
// This matches the logic in AcpiTimerLibConstructor ().
|
||||
//
|
||||
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
|
||||
//
|
||||
// The PEI phase should be exited with fully accessibe ACPI PM IO space:
|
||||
// 1. set PMBA
|
||||
//
|
||||
PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
|
||||
|
||||
//
|
||||
// 2. set PCICMD/IOSE
|
||||
//
|
||||
PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
|
||||
|
||||
//
|
||||
// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
|
||||
//
|
||||
PciOr8 (AcpiCtlReg, AcpiEnBit);
|
||||
}
|
||||
|
||||
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
|
||||
//
|
||||
// Set Root Complex Register Block BAR
|
||||
//
|
||||
PciWrite32 (
|
||||
POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
|
||||
ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
|
||||
);
|
||||
|
||||
//
|
||||
// Set PCI Express Register Range Base Address
|
||||
//
|
||||
PciExBarInitialization ();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
BootModeInitialization (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
if (CmosRead8 (0xF) == 0xFE) {
|
||||
mBootMode = BOOT_ON_S3_RESUME;
|
||||
}
|
||||
CmosWrite8 (0xF, 0x00);
|
||||
|
||||
Status = PeiServicesSetBootMode (mBootMode);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
Status = PeiServicesInstallPpi (mPpiBootMode);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ReserveEmuVariableNvStore (
|
||||
)
|
||||
{
|
||||
EFI_PHYSICAL_ADDRESS VariableStore;
|
||||
RETURN_STATUS PcdStatus;
|
||||
|
||||
//
|
||||
// Allocate storage for NV variables early on so it will be
|
||||
// at a consistent address. Since VM memory is preserved
|
||||
// across reboots, this allows the NV variable storage to survive
|
||||
// a VM reboot.
|
||||
//
|
||||
VariableStore =
|
||||
(EFI_PHYSICAL_ADDRESS)(UINTN)
|
||||
AllocateRuntimePages (
|
||||
EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
|
||||
);
|
||||
DEBUG ((DEBUG_INFO,
|
||||
"Reserved variable store memory: 0x%lX; size: %dkb\n",
|
||||
VariableStore,
|
||||
(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
|
||||
));
|
||||
PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
DebugDumpCmos (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 Loop;
|
||||
|
||||
DEBUG ((DEBUG_INFO, "CMOS:\n"));
|
||||
|
||||
for (Loop = 0; Loop < 0x80; Loop++) {
|
||||
if ((Loop % 0x10) == 0) {
|
||||
DEBUG ((DEBUG_INFO, "%02x:", Loop));
|
||||
}
|
||||
DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
|
||||
if ((Loop % 0x10) == 0xf) {
|
||||
DEBUG ((DEBUG_INFO, "\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
Perform Platform PEI initialization.
|
||||
|
||||
@param FileHandle Handle of the file being invoked.
|
||||
@param PeiServices Describes the list of possible PEI Services.
|
||||
|
||||
@return EFI_SUCCESS The PEIM initialized successfully.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
InitializeXenPlatform (
|
||||
IN EFI_PEI_FILE_HANDLE FileHandle,
|
||||
IN CONST EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
{
|
||||
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
|
||||
|
||||
DebugDumpCmos ();
|
||||
|
||||
if (!XenDetect ()) {
|
||||
DEBUG ((DEBUG_ERROR, "ERROR: Xen isn't detected\n"));
|
||||
ASSERT (FALSE);
|
||||
CpuDeadLoop ();
|
||||
}
|
||||
|
||||
BootModeInitialization ();
|
||||
AddressWidthInitialization ();
|
||||
|
||||
//
|
||||
// Query Host Bridge DID
|
||||
//
|
||||
mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
|
||||
|
||||
PublishPeiMemory ();
|
||||
|
||||
InitializeRamRegions ();
|
||||
|
||||
InitializeXen ();
|
||||
|
||||
if (mBootMode != BOOT_ON_S3_RESUME) {
|
||||
ReserveEmuVariableNvStore ();
|
||||
PeiFvInitialization ();
|
||||
MemMapInitialization ();
|
||||
}
|
||||
|
||||
InstallClearCacheCallback ();
|
||||
AmdSevInitialize ();
|
||||
MiscInitialization ();
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/** @file
|
||||
Platform PEI module include file.
|
||||
|
||||
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2019, Citrix Systems, Inc.
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _PLATFORM_PEI_H_INCLUDED_
|
||||
#define _PLATFORM_PEI_H_INCLUDED_
|
||||
|
||||
#include <IndustryStandard/E820.h>
|
||||
|
||||
VOID
|
||||
AddIoMemoryBaseSizeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
UINT64 MemorySize
|
||||
);
|
||||
|
||||
VOID
|
||||
AddIoMemoryRangeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
EFI_PHYSICAL_ADDRESS MemoryLimit
|
||||
);
|
||||
|
||||
VOID
|
||||
AddMemoryBaseSizeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
UINT64 MemorySize
|
||||
);
|
||||
|
||||
VOID
|
||||
AddMemoryRangeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
EFI_PHYSICAL_ADDRESS MemoryLimit
|
||||
);
|
||||
|
||||
VOID
|
||||
AddReservedMemoryBaseSizeHob (
|
||||
EFI_PHYSICAL_ADDRESS MemoryBase,
|
||||
UINT64 MemorySize,
|
||||
BOOLEAN Cacheable
|
||||
);
|
||||
|
||||
VOID
|
||||
AddressWidthInitialization (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
Q35TsegMbytesInitialization (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PublishPeiMemory (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINT32
|
||||
GetSystemMemorySizeBelow4gb (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
InitializeRamRegions (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PeiFvInitialization (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
InstallClearCacheCallback (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
InitializeXen (
|
||||
VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
XenDetect (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
AmdSevInitialize (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
XenPublishRamRegions (
|
||||
VOID
|
||||
);
|
||||
|
||||
extern EFI_BOOT_MODE mBootMode;
|
||||
|
||||
extern UINT8 mPhysMemAddressWidth;
|
||||
|
||||
extern UINT16 mHostBridgeDevId;
|
||||
|
||||
#endif // _PLATFORM_PEI_H_INCLUDED_
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
/**@file
|
||||
Xen Platform PEI support
|
||||
|
||||
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
|
||||
Copyright (c) 2019, Citrix Systems, Inc.
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
//
|
||||
// The package level header files this module uses
|
||||
//
|
||||
#include <PiPei.h>
|
||||
|
||||
//
|
||||
// The Library classes this module consumes
|
||||
//
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/HobLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Guid/XenInfo.h>
|
||||
#include <IndustryStandard/E820.h>
|
||||
#include <Library/ResourcePublicationLib.h>
|
||||
#include <Library/MtrrLib.h>
|
||||
|
||||
#include "Platform.h"
|
||||
#include "Xen.h"
|
||||
|
||||
STATIC UINT32 mXenLeaf = 0;
|
||||
|
||||
EFI_XEN_INFO mXenInfo;
|
||||
|
||||
/**
|
||||
Returns E820 map provided by Xen
|
||||
|
||||
@param Entries Pointer to E820 map
|
||||
@param Count Number of entries
|
||||
|
||||
@return EFI_STATUS
|
||||
**/
|
||||
EFI_STATUS
|
||||
XenGetE820Map (
|
||||
EFI_E820_ENTRY64 **Entries,
|
||||
UINT32 *Count
|
||||
)
|
||||
{
|
||||
EFI_XEN_OVMF_INFO *Info =
|
||||
(EFI_XEN_OVMF_INFO *)(UINTN) OVMF_INFO_PHYSICAL_ADDRESS;
|
||||
|
||||
if (AsciiStrCmp ((CHAR8 *) Info->Signature, "XenHVMOVMF")) {
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
ASSERT (Info->E820 < MAX_ADDRESS);
|
||||
*Entries = (EFI_E820_ENTRY64 *)(UINTN) Info->E820;
|
||||
*Count = Info->E820EntriesCount;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Connects to the Hypervisor.
|
||||
|
||||
@param XenLeaf CPUID index used to connect.
|
||||
|
||||
@return EFI_STATUS
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
XenConnect (
|
||||
UINT32 XenLeaf
|
||||
)
|
||||
{
|
||||
UINT32 Index;
|
||||
UINT32 TransferReg;
|
||||
UINT32 TransferPages;
|
||||
UINT32 XenVersion;
|
||||
|
||||
AsmCpuid (XenLeaf + 2, &TransferPages, &TransferReg, NULL, NULL);
|
||||
mXenInfo.HyperPages = AllocatePages (TransferPages);
|
||||
if (!mXenInfo.HyperPages) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
}
|
||||
|
||||
for (Index = 0; Index < TransferPages; Index++) {
|
||||
AsmWriteMsr64 (TransferReg,
|
||||
(UINTN) mXenInfo.HyperPages +
|
||||
(Index << EFI_PAGE_SHIFT) + Index);
|
||||
}
|
||||
|
||||
AsmCpuid (XenLeaf + 1, &XenVersion, NULL, NULL, NULL);
|
||||
DEBUG ((DEBUG_ERROR, "Detected Xen version %d.%d\n",
|
||||
XenVersion >> 16, XenVersion & 0xFFFF));
|
||||
mXenInfo.VersionMajor = (UINT16)(XenVersion >> 16);
|
||||
mXenInfo.VersionMinor = (UINT16)(XenVersion & 0xFFFF);
|
||||
|
||||
/* TBD: Locate hvm_info and reserve it away. */
|
||||
mXenInfo.HvmInfo = NULL;
|
||||
|
||||
BuildGuidDataHob (
|
||||
&gEfiXenInfoGuid,
|
||||
&mXenInfo,
|
||||
sizeof(mXenInfo)
|
||||
);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Figures out if we are running inside Xen HVM.
|
||||
|
||||
@retval TRUE Xen was detected
|
||||
@retval FALSE Xen was not detected
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
XenDetect (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT8 Signature[13];
|
||||
|
||||
if (mXenLeaf != 0) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
Signature[12] = '\0';
|
||||
for (mXenLeaf = 0x40000000; mXenLeaf < 0x40010000; mXenLeaf += 0x100) {
|
||||
AsmCpuid (mXenLeaf,
|
||||
NULL,
|
||||
(UINT32 *) &Signature[0],
|
||||
(UINT32 *) &Signature[4],
|
||||
(UINT32 *) &Signature[8]);
|
||||
|
||||
if (!AsciiStrCmp ((CHAR8 *) Signature, "XenVMMXenVMM")) {
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
mXenLeaf = 0;
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
XenPublishRamRegions (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_E820_ENTRY64 *E820Map;
|
||||
UINT32 E820EntriesCount;
|
||||
EFI_STATUS Status;
|
||||
|
||||
DEBUG ((DEBUG_INFO, "Using memory map provided by Xen\n"));
|
||||
|
||||
//
|
||||
// Parse RAM in E820 map
|
||||
//
|
||||
E820EntriesCount = 0;
|
||||
Status = XenGetE820Map (&E820Map, &E820EntriesCount);
|
||||
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
if (E820EntriesCount > 0) {
|
||||
EFI_E820_ENTRY64 *Entry;
|
||||
UINT32 Loop;
|
||||
|
||||
for (Loop = 0; Loop < E820EntriesCount; Loop++) {
|
||||
Entry = E820Map + Loop;
|
||||
|
||||
//
|
||||
// Only care about RAM
|
||||
//
|
||||
if (Entry->Type != EfiAcpiAddressRangeMemory) {
|
||||
continue;
|
||||
}
|
||||
|
||||
AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);
|
||||
|
||||
MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Perform Xen PEI initialization.
|
||||
|
||||
@return EFI_SUCCESS Xen initialized successfully
|
||||
@return EFI_NOT_FOUND Not running under Xen
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
InitializeXen (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
RETURN_STATUS PcdStatus;
|
||||
|
||||
if (mXenLeaf == 0) {
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
XenConnect (mXenLeaf);
|
||||
|
||||
//
|
||||
// Reserve away HVMLOADER reserved memory [0xFC000000,0xFD000000).
|
||||
// This needs to match HVMLOADER RESERVED_MEMBASE/RESERVED_MEMSIZE.
|
||||
//
|
||||
AddReservedMemoryBaseSizeHob (0xFC000000, 0x1000000, FALSE);
|
||||
|
||||
PcdStatus = PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);
|
||||
ASSERT_RETURN_ERROR (PcdStatus);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/** @file
|
||||
Ovmf info structure passed by Xen
|
||||
|
||||
Copyright (c) 2013, Citrix Systems UK Ltd.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __XEN_H__
|
||||
#define __XEN_H__
|
||||
|
||||
#include <PiPei.h>
|
||||
|
||||
// Physical address of OVMF info
|
||||
#define OVMF_INFO_PHYSICAL_ADDRESS 0x00001000
|
||||
|
||||
// This structure must match the definition on Xen side
|
||||
#pragma pack(1)
|
||||
typedef struct {
|
||||
CHAR8 Signature[14]; // XenHVMOVMF\0
|
||||
UINT8 Length; // Length of this structure
|
||||
UINT8 Checksum; // Set such that the sum over bytes 0..length == 0
|
||||
//
|
||||
// Physical address of an array of TablesCount elements.
|
||||
//
|
||||
// Each element contains the physical address of a BIOS table.
|
||||
//
|
||||
EFI_PHYSICAL_ADDRESS Tables;
|
||||
UINT32 TablesCount;
|
||||
//
|
||||
// Physical address of the E820 table, contains E820EntriesCount entries.
|
||||
//
|
||||
EFI_PHYSICAL_ADDRESS E820;
|
||||
UINT32 E820EntriesCount;
|
||||
} EFI_XEN_OVMF_INFO;
|
||||
#pragma pack()
|
||||
|
||||
#endif /* __XEN_H__ */
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
## @file
|
||||
# Platform PEI driver
|
||||
#
|
||||
# This module provides platform specific function to detect boot mode.
|
||||
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2019, Citrix Systems, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = XenPlatformPei
|
||||
FILE_GUID = f112a6ee-993a-4f0b-8295-e52029d9b4ba
|
||||
MODULE_TYPE = PEIM
|
||||
VERSION_STRING = 1.0
|
||||
ENTRY_POINT = InitializeXenPlatform
|
||||
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC
|
||||
#
|
||||
|
||||
[Sources]
|
||||
AmdSev.c
|
||||
ClearCache.c
|
||||
Cmos.c
|
||||
Cmos.h
|
||||
Fv.c
|
||||
MemDetect.c
|
||||
Platform.c
|
||||
Platform.h
|
||||
Xen.c
|
||||
Xen.h
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
SecurityPkg/SecurityPkg.dec
|
||||
UefiCpuPkg/UefiCpuPkg.dec
|
||||
OvmfPkg/OvmfPkg.dec
|
||||
|
||||
[Guids]
|
||||
gEfiMemoryTypeInformationGuid
|
||||
gEfiXenInfoGuid
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
CacheMaintenanceLib
|
||||
DebugLib
|
||||
HobLib
|
||||
IoLib
|
||||
PciLib
|
||||
ResourcePublicationLib
|
||||
PeiServicesLib
|
||||
PeimEntryPoint
|
||||
MtrrLib
|
||||
MemEncryptSevLib
|
||||
PcdLib
|
||||
|
||||
[Pcd]
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
|
||||
gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy
|
||||
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
|
||||
|
||||
[FixedPcd]
|
||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
|
||||
|
||||
[Ppis]
|
||||
gEfiPeiMasterBootModePpiGuid
|
||||
gEfiPeiMpServicesPpiGuid
|
||||
|
||||
[Depex]
|
||||
TRUE
|
||||
|
||||
Loading…
Reference in New Issue