mirror of https://github.com/acidanthera/audk.git
OvmfPkg: SmmCpuFeaturesLib: implement SMRAM state save map access
This implementation copies SMRAM state save map access from the PiSmmCpuDxeSmm module. The most notable change is: - dropping support for EFI_SMM_SAVE_STATE_REGISTER_IO - changing the implementation of EFI_SMM_SAVE_STATE_REGISTER_LMA to use the SMM revision id instead of a local variable (which UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c initializes from CPUID's LM bit). This accounts for QEMU's implementation of x86_64, which always uses revision 0x20064 even if the LM bit is zero. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [lersek@redhat.com: reflow commit message & fix typo, convert patch to CRLF] Cc: Paolo Bonzini <pbonzini@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19056 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Paolo Bonzini
lersek
parent
d7e71b2925
commit
4036b4e57c
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@ -15,11 +15,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include <PiSmm.h>
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#include <PiSmm.h>
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PcdLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DebugLib.h>
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#include <Register/SmramSaveStateMap.h>
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#include <Register/SmramSaveStateMap.h>
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//
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// EFER register LMA bit
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//
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#define LMA BIT10
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/**
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/**
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The constructor function
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The constructor function
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@ -128,7 +135,35 @@ SmmCpuFeaturesHookReturnFromSmm (
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IN UINT64 NewInstructionPointer
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IN UINT64 NewInstructionPointer
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)
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)
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{
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{
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return 0;
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UINT64 OriginalInstructionPointer;
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SMRAM_SAVE_STATE_MAP *CpuSaveState = (SMRAM_SAVE_STATE_MAP *)CpuState;
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
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CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
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CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
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}
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} else {
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OriginalInstructionPointer = CpuSaveState->x64._RIP;
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if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
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CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
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} else {
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CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
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}
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
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CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
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}
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}
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return OriginalInstructionPointer;
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}
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}
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/**
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/**
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@ -359,6 +394,213 @@ SmmCpuFeaturesSetSmmRegister (
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ASSERT (FALSE);
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ASSERT (FALSE);
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}
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}
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///
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/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
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///
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#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
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///
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/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
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///
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#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
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///
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/// Structure used to describe a range of registers
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///
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typedef struct {
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EFI_SMM_SAVE_STATE_REGISTER Start;
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EFI_SMM_SAVE_STATE_REGISTER End;
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UINTN Length;
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} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
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///
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/// Structure used to build a lookup table to retrieve the widths and offsets
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/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
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///
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#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
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typedef struct {
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UINT8 Width32;
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UINT8 Width64;
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UINT16 Offset32;
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UINT16 Offset64Lo;
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UINT16 Offset64Hi;
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BOOLEAN Writeable;
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} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
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///
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/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
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/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
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///
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static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
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SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
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SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
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SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
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{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
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};
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///
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/// Lookup table used to retrieve the widths and offsets associated with each
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/// supported EFI_SMM_SAVE_STATE_REGISTER value
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///
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static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
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{0, 0, 0, 0, 0, FALSE}, // Reserved
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//
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// CPU Save State registers defined in PI SMM CPU Protocol.
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//
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{0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
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{0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
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{0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
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{4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
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{4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
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{4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
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{4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
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{4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
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{4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
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{0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
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{4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
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{4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
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{4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
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{0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
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{4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
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{4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
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{4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
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{4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
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{4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
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{4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
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{4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
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{4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
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{4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
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{4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
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{4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
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{4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
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{0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
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};
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//
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// No support for I/O restart
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//
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/**
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Read information from the CPU save state.
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@param Register Specifies the CPU register to read form the save state.
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@retval 0 Register is not valid
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@retval >0 Index into mSmmCpuWidthOffset[] associated with Register
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**/
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static UINTN
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GetRegisterIndex (
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IN EFI_SMM_SAVE_STATE_REGISTER Register
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)
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{
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UINTN Index;
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UINTN Offset;
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for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
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if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {
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return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
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}
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Offset += mSmmCpuRegisterRanges[Index].Length;
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}
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return 0;
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}
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/**
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Read a CPU Save State register on the target processor.
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This function abstracts the differences that whether the CPU Save State register is in the
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IA32 CPU Save State Map or X64 CPU Save State Map.
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This function supports reading a CPU Save State register in SMBase relocation handler.
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@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
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@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
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@param[in] Width The number of bytes to read from the CPU save state.
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@param[out] Buffer Upon return, this holds the CPU register value read from the save state.
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@retval EFI_SUCCESS The register was read from Save State.
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@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
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@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
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**/
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static EFI_STATUS
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ReadSaveStateRegisterByIndex (
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IN UINTN CpuIndex,
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IN UINTN RegisterIndex,
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IN UINTN Width,
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OUT VOID *Buffer
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)
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{
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SMRAM_SAVE_STATE_MAP *CpuSaveState;
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CpuSaveState = gSmst->CpuSaveState[CpuIndex];
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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//
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// If 32-bit mode width is zero, then the specified register can not be accessed
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//
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if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
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return EFI_NOT_FOUND;
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}
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//
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// If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
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//
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if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Write return buffer
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//
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ASSERT(CpuSaveState != NULL);
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CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
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} else {
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//
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// If 64-bit mode width is zero, then the specified register can not be accessed
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//
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if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
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return EFI_NOT_FOUND;
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}
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//
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// If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
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//
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if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Write lower 32-bits of return buffer
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//
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CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
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if (Width >= 4) {
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//
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// Write upper 32-bits of return buffer
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//
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CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
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}
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}
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return EFI_SUCCESS;
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||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Read an SMM Save State register on the target processor. If this function
|
Read an SMM Save State register on the target processor. If this function
|
||||||
returns EFI_UNSUPPORTED, then the caller is responsible for reading the
|
returns EFI_UNSUPPORTED, then the caller is responsible for reading the
|
||||||
|
|
@ -386,7 +628,52 @@ SmmCpuFeaturesReadSaveStateRegister (
|
||||||
OUT VOID *Buffer
|
OUT VOID *Buffer
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
return EFI_UNSUPPORTED;
|
UINTN RegisterIndex;
|
||||||
|
SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
|
||||||
|
//
|
||||||
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
|
||||||
|
//
|
||||||
|
// Only byte access is supported for this register
|
||||||
|
//
|
||||||
|
if (Width != 1) {
|
||||||
|
return EFI_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
|
||||||
|
|
||||||
|
//
|
||||||
|
// Check CPU mode
|
||||||
|
//
|
||||||
|
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
|
||||||
|
*(UINT8 *)Buffer = 32;
|
||||||
|
} else {
|
||||||
|
*(UINT8 *)Buffer = 64;
|
||||||
|
}
|
||||||
|
|
||||||
|
return EFI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
|
||||||
|
//
|
||||||
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Convert Register to a register lookup table index. Let
|
||||||
|
// PiSmmCpuDxeSmm implement other special registers (currently
|
||||||
|
// there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
|
||||||
|
//
|
||||||
|
RegisterIndex = GetRegisterIndex (Register);
|
||||||
|
if (RegisterIndex == 0) {
|
||||||
|
return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -414,7 +701,91 @@ SmmCpuFeaturesWriteSaveStateRegister (
|
||||||
IN CONST VOID *Buffer
|
IN CONST VOID *Buffer
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
UINTN RegisterIndex;
|
||||||
|
SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
|
||||||
|
//
|
||||||
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
|
||||||
|
return EFI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
|
||||||
|
//
|
||||||
|
if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Convert Register to a register lookup table index. Let
|
||||||
|
// PiSmmCpuDxeSmm implement other special registers (currently
|
||||||
|
// there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
|
||||||
|
//
|
||||||
|
RegisterIndex = GetRegisterIndex (Register);
|
||||||
|
if (RegisterIndex == 0) {
|
||||||
|
return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
|
||||||
|
|
||||||
|
//
|
||||||
|
// Do not write non-writable SaveState, because it will cause exception.
|
||||||
|
//
|
||||||
|
if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
|
||||||
return EFI_UNSUPPORTED;
|
return EFI_UNSUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Check CPU mode
|
||||||
|
//
|
||||||
|
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
|
||||||
|
//
|
||||||
|
// If 32-bit mode width is zero, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
|
||||||
|
return EFI_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
//
|
||||||
|
// Write SMM State register
|
||||||
|
//
|
||||||
|
ASSERT (CpuSaveState != NULL);
|
||||||
|
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// If 64-bit mode width is zero, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
|
||||||
|
return EFI_NOT_FOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
|
||||||
|
//
|
||||||
|
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
|
||||||
|
return EFI_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Write lower 32-bits of SMM State register
|
||||||
|
//
|
||||||
|
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
|
||||||
|
if (Width >= 4) {
|
||||||
|
//
|
||||||
|
// Write upper 32-bits of SMM State register
|
||||||
|
//
|
||||||
|
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return EFI_SUCCESS;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
|
|
@ -31,5 +31,7 @@
|
||||||
|
|
||||||
[LibraryClasses]
|
[LibraryClasses]
|
||||||
BaseLib
|
BaseLib
|
||||||
|
BaseMemoryLib
|
||||||
PcdLib
|
PcdLib
|
||||||
DebugLib
|
DebugLib
|
||||||
|
SmmServicesTableLib
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue