mirror of https://github.com/acidanthera/audk.git
OvmfPkg: SmmCpuFeaturesLib: remove unnecessary bits
SMRR, MTRR, and SMM Feature Control support is not needed on a virtual platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: insert space between ASSERT and (), convert to CRLF, refresh against SVN r18958] Cc: Paolo Bonzini <pbonzini@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19055 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Paolo Bonzini
lersek
parent
86d71589c1
commit
d7e71b2925
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@ -15,58 +15,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include <PiSmm.h>
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Library/BaseLib.h>
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#include <Library/MtrrLib.h>
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#include <Library/PcdLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/DebugLib.h>
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#include <Register/Cpuid.h>
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#include <Register/SmramSaveStateMap.h>
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//
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// Machine Specific Registers (MSRs)
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//
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#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
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#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
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#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
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#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
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#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
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#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
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#define EFI_MSR_SMRR_MASK 0xFFFFF000
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#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
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#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
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//
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// MSRs required for configuration of SMM Code Access Check
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//
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#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
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#define SMM_CODE_ACCESS_CHK_BIT BIT58
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//
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// Set default value to assume SMRR is not supported
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//
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BOOLEAN mSmrrSupported = FALSE;
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//
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// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
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//
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BOOLEAN mSmmFeatureControlSupported = FALSE;
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//
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// Set default value to assume IA-32 Architectural MSRs are used
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//
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UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
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UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
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//
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// Set default value to assume MTRRs need to be configured on each SMI
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//
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BOOLEAN mNeedConfigureMtrrs = TRUE;
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//
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// Array for state of SMRR enable on all CPUs
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//
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BOOLEAN *mSmrrEnabled;
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/**
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The constructor function
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@ -83,91 +36,9 @@ SmmCpuFeaturesLibConstructor (
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN FamilyId;
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UINTN ModelId;
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//
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// Retrieve CPU Family and Model
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// No need to program SMRRs on our virtual platform.
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//
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AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if (FamilyId == 0x06 || FamilyId == 0x0f) {
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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}
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//
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// Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
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//
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if ((RegEdx & BIT12) != 0) {
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//
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// Check MTRR_CAP MSR bit 11 for SMRR support
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
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mSmrrSupported = TRUE;
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
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//
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// If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
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// SMRR Physical Base and SMM Physical Mask MSRs are not available.
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//
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if (FamilyId == 0x06) {
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if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {
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mSmrrSupported = FALSE;
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
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//
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// If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
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// Processor Family MSRs
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//
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if (FamilyId == 0x06) {
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if (ModelId == 0x17 || ModelId == 0x0f) {
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mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
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mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
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}
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 34.4.2 SMRAM Caching
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// An IA-32 processor does not automatically write back and invalidate its
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// caches before entering SMM or before exiting SMM. Because of this behavior,
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// care must be taken in the placement of the SMRAM in system memory and in
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// the caching of the SMRAM to prevent cache incoherence when switching back
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// and forth between SMM and protected mode operation.
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//
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// An IA-32 processor is a processor that does not support the Intel 64
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// Architecture. Support for the Intel 64 Architecture can be detected from
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// CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]
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//
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// If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,
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// so caches are flushed on SMI entry and SMI exit, the interrupted code
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// MTRRs are saved/restored, and MTRRs for SMM are loaded.
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//
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AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
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if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
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AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT29) != 0) {
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mNeedConfigureMtrrs = FALSE;
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}
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}
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//
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// Allocate array for state of SMRR enable on all CPUs
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//
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mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
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ASSERT (mSmrrEnabled != NULL);
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return EFI_SUCCESS;
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}
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@ -205,11 +76,6 @@ SmmCpuFeaturesInitializeProcessor (
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)
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{
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SMRAM_SAVE_STATE_MAP *CpuState;
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UINT64 FeatureControl;
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN FamilyId;
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UINTN ModelId;
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//
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// Configure SMBASE.
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@ -218,67 +84,8 @@ SmmCpuFeaturesInitializeProcessor (
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CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
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// No need to program SMRRs on our virtual platform.
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//
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// If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then
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// make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
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// accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
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// is set, then the MSR is locked and can not be modified.
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//
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if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {
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FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
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if ((FeatureControl & BIT3) == 0) {
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if ((FeatureControl & BIT0) == 0) {
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AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);
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} else {
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mSmrrSupported = FALSE;
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}
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}
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}
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//
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// If SMRR is supported, then program SMRR base/mask MSRs.
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// The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
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// The code that initializes SMM environment is running in normal mode
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// from SMRAM region. If SMRR is enabled here, then the SMRAM region
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// is protected and the normal mode code execution will fail.
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//
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if (mSmrrSupported) {
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AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);
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AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));
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mSmrrEnabled[CpuIndex] = FALSE;
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}
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//
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// Retrieve CPU Family and Model
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//
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AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
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FamilyId = (RegEax >> 8) & 0xf;
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ModelId = (RegEax >> 4) & 0xf;
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if (FamilyId == 0x06 || FamilyId == 0x0f) {
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ModelId = ModelId | ((RegEax >> 12) & 0xf0);
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}
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
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// Processor Family.
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//
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// If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
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// Intel(R) Core(TM) Processor Family MSRs.
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//
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if (FamilyId == 0x06) {
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if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
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//
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// Check to see if the CPU supports the SMM Code Access Check feature
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// Do not access this MSR unless the CPU supports the SmmRegFeatureControl
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//
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if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {
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mSmmFeatureControlSupported = TRUE;
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}
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}
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}
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}
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/**
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@ -413,7 +220,7 @@ SmmCpuFeaturesNeedConfigureMtrrs (
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VOID
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)
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{
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return mNeedConfigureMtrrs;
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return FALSE;
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}
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/**
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@ -426,9 +233,9 @@ SmmCpuFeaturesDisableSmrr (
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VOID
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)
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{
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if (mSmrrSupported && mNeedConfigureMtrrs) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
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}
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//
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// No SMRR support, nothing to do
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//
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}
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/**
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@ -441,9 +248,9 @@ SmmCpuFeaturesReenableSmrr (
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VOID
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)
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{
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if (mSmrrSupported && mNeedConfigureMtrrs) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
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}
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//
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// No SMRR support, nothing to do
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//
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}
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/**
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@ -460,12 +267,8 @@ SmmCpuFeaturesRendezvousEntry (
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)
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{
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//
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// If SMRR is supported and this is the first normal SMI, then enable SMRR
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// No SMRR support, nothing to do
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//
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if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) {
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AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
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mSmrrEnabled[CpuIndex] = TRUE;
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}
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}
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/**
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@ -503,9 +306,7 @@ SmmCpuFeaturesIsSmmRegisterSupported (
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IN SMM_REG_NAME RegName
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)
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{
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if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
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return TRUE;
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}
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ASSERT (RegName == SmmRegFeatureControl);
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return FALSE;
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}
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@ -528,9 +329,11 @@ SmmCpuFeaturesGetSmmRegister (
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IN SMM_REG_NAME RegName
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)
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{
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if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
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return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
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}
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//
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// This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
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// The last of these should actually be SmmRegSmmDisable, so we can just
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// return FALSE.
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//
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return 0;
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}
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@ -553,9 +356,7 @@ SmmCpuFeaturesSetSmmRegister (
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IN UINT64 Value
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)
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{
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if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
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AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
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}
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ASSERT (FALSE);
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}
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/**
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@ -32,8 +32,4 @@
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[LibraryClasses]
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BaseLib
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PcdLib
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MemoryAllocationLib
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DebugLib
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[Pcd]
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES
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