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EmbeddedPkg/Lan9118Dxe: remove redundant stalls 

Now that the LAN9118-specific MMIO accessors provide the required
delays, remove the redundant stalls.

Stalls in delay loops are kept, as these give time for work to happen
beyond synchronisation of the device register file.

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Mark Rutland 2016-05-06 18:19:09 +01:00 committed by Ard Biesheuvel
parent e68449c999
commit 505e7fd5d0
2 changed files with 0 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c
View File

@ -307,8 +307,6 @@ SnpInitialize (
// Write the current configuration to the register
Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf);
gBS->Stall (LAN9118_STALL);
gBS->Stall (LAN9118_STALL);
// Configure GPIO and HW
Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);
@ -431,7 +429,6 @@ SnpReset (
// Write the current configuration to the register
Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf);
gBS->Stall (LAN9118_STALL);
// Reactivate the LEDs
Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);
@ -446,7 +443,6 @@ SnpReset (
HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize
Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf
gBS->Stall (LAN9118_STALL);
}
// Enable the receiver and transmitter and clear their contents
@ -701,7 +697,6 @@ SnpReceiveFilters (
// Write the options to the MAC_CSR
//
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCSRValue);
gBS->Stall (LAN9118_STALL);
//
// If we have to retrieve something, start packet reception.

16
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c
View File

@ -284,7 +284,6 @@ IndirectEEPROMRead32 (
// Write to Eeprom command register
Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
gBS->Stall (LAN9118_STALL);
// Wait until operation has completed
while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
@ -332,7 +331,6 @@ IndirectEEPROMWrite32 (
// Write to Eeprom command register
Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);
gBS->Stall (LAN9118_STALL);
// Wait until operation has completed
while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);
@ -410,7 +408,6 @@ Lan9118Initialize (
if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {
DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));
Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);
gBS->Stall (LAN9118_STALL);
}
// Check that device is active
@ -495,7 +492,6 @@ SoftReset (
// Write the configuration
Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);
gBS->Stall (LAN9118_STALL);
// Wait for reset to complete
while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {
@ -590,7 +586,6 @@ ConfigureHardware (
// Write the configuration
Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);
gBS->Stall (LAN9118_STALL);
}
return EFI_SUCCESS;
@ -719,7 +714,6 @@ StopTx (
TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
gBS->Stall (LAN9118_STALL);
}
// Check if already stopped
@ -738,7 +732,6 @@ StopTx (
if (TxCfg & TXCFG_TX_ON) {
TxCfg |= TXCFG_STOP_TX;
Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
gBS->Stall (LAN9118_STALL);
// Wait for Tx to finish transmitting
while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);
@ -773,7 +766,6 @@ StopRx (
RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);
RxCfg |= RXCFG_RX_DUMP;
Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);
gBS->Stall (LAN9118_STALL);
while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
}
@ -799,28 +791,23 @@ StartTx (
TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;
Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
gBS->Stall (LAN9118_STALL);
}
// Check if tx was started from MAC and enable if not
if (Flags & START_TX_MAC) {
MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);
gBS->Stall (LAN9118_STALL);
if ((MacCsr & MACCR_TX_EN) == 0) {
MacCsr |= MACCR_TX_EN;
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
gBS->Stall (LAN9118_STALL);
}
}
// Check if tx was started from TX_CFG and enable if not
if (Flags & START_TX_CFG) {
TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);
gBS->Stall (LAN9118_STALL);
if ((TxCfg & TXCFG_TX_ON) == 0) {
TxCfg |= TXCFG_TX_ON;
Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);
gBS->Stall (LAN9118_STALL);
}
}
@ -850,14 +837,12 @@ StartRx (
RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);
RxCfg |= RXCFG_RX_DUMP;
Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);
gBS->Stall (LAN9118_STALL);
while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);
}
MacCsr |= MACCR_RX_EN;
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);
gBS->Stall (LAN9118_STALL);
}
return EFI_SUCCESS;
@ -1047,7 +1032,6 @@ ChangeFifoAllocation (
HwConf &= ~(0xF0000);
HwConf |= ((TxFifoOption & 0xF) << 16);
Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);
gBS->Stall (LAN9118_STALL);
return EFI_SUCCESS;
}