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UefiCpuPkg/PiSmmCpu: Always set WP in CR0 

So that we can use write-protection for code later.

It is REPOST.
It includes suggestion from Michael Kinney <michael.d.kinney@intel.com>:
- "For IA32 assembly, can we combine into a single OR instruction that
  sets both page enable and WP?"
- "For X64, does it make sense to use single OR instruction instead of 2
  BTS instructions as well?"

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Suggested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19068 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Yao, Jiewen 2015-11-30 19:57:45 +00:00 committed by lersek
parent 881520ea67
commit 53ba3fb8aa
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
View File

@ -123,7 +123,7 @@ L11:
L12: # as cr4.PGE is not set here, refresh cr3 L12: # as cr4.PGE is not set here, refresh cr3
movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB. movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
movl %cr0, %ebx movl %cr0, %ebx
orl $0x080000000, %ebx # enable paging orl $0x080010000, %ebx # enable paging + WP
movl %ebx, %cr0 movl %ebx, %cr0
leal DSC_OFFSET(%edi),%ebx leal DSC_OFFSET(%edi),%ebx
movw DSC_DS(%ebx),%ax movw DSC_DS(%ebx),%ax

2
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
View File

@ -129,7 +129,7 @@ gSmiCr3 DD ?
@@: ; as cr4.PGE is not set here, refresh cr3 @@: ; as cr4.PGE is not set here, refresh cr3
mov cr4, eax ; in PreModifyMtrrs() to flush TLB. mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
mov ebx, cr0 mov ebx, cr0
or ebx, 080000000h ; enable paging or ebx, 080010000h ; enable paging + WP
mov cr0, ebx mov cr0, ebx
lea ebx, [edi + DSC_OFFSET] lea ebx, [edi + DSC_OFFSET]
mov ax, [ebx + DSC_DS] mov ax, [ebx + DSC_DS]

2
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
View File

@ -144,7 +144,7 @@ Base:
orb $1,%ah orb $1,%ah
wrmsr wrmsr
movq %cr0, %rbx movq %cr0, %rbx
btsl $31, %ebx orl $0x080010000, %ebx # enable paging + WP
movq %rbx, %cr0 movq %rbx, %cr0
retf retf
LongMode: # long mode (64-bit code) starts here LongMode: # long mode (64-bit code) starts here

2
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
View File

@ -140,7 +140,7 @@ Base:
or ah, 1 or ah, 1
wrmsr wrmsr
mov rbx, cr0 mov rbx, cr0
bts ebx, 31 or ebx, 080010000h ; enable paging + WP
mov cr0, rbx mov cr0, rbx
retf retf
@LongMode: ; long mode (64-bit code) starts here @LongMode: ; long mode (64-bit code) starts here