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ArmPkg: Retire ArmDisassemblerLib
No longer used anywhere so can be retired. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel
mergify[bot]
parent
fbe19844e0
commit
62cd7d338b
@ -28,10 +28,6 @@
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Include # Root include for the package
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[LibraryClasses.common]
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## @libraryclass Convert Arm instructions to a human readable format.
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#
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ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
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## @libraryclass Provides an interface to Arm generic counters.
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#
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ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
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@ -110,7 +110,6 @@
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[Components.common]
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ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
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ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
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ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
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ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
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ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
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@ -1,37 +0,0 @@
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/** @file
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_DISASSEMBLER_LIB_H_
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#define ARM_DISASSEMBLER_LIB_H_
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/**
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Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instruction.
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We cheat and only decode instructions that access
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memory. If the instruction is not found we dump the instruction in hex.
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@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
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@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
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@param Extended TRUE dump hex for instruction too.
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@param ItBlock Size of IT Block
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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**/
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VOID
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DisassembleInstruction (
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IN UINT8 **OpCodePtr,
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IN BOOLEAN Thumb,
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IN BOOLEAN Extended,
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IN OUT UINT32 *ItBlock,
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OUT CHAR8 *Buf,
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OUT UINTN Size
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);
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#endif // ARM_DISASSEMBLER_LIB_H_
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@ -1,42 +0,0 @@
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/** @file
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Default exception handler
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Copyright (c) 2014, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/PrintLib.h>
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#include <Library/ArmDisassemblerLib.h>
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/**
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Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instruction.
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@param OpCodePtrPtr Pointer to pointer of instruction to disassemble.
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@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
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@param Extended TRUE dump hex for instruction too.
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@param ItBlock Size of IT Block
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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**/
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VOID
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DisassembleInstruction (
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IN UINT8 **OpCodePtr,
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IN BOOLEAN Thumb,
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IN BOOLEAN Extended,
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IN OUT UINT32 *ItBlock,
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OUT CHAR8 *Buf,
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OUT UINTN Size
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)
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{
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// Not yet supported for AArch64.
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// Put error in the buffer as we have no return code and the buffer may be
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// printed directly so needs a '\0'.
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AsciiSPrint (Buf, Size, "AArch64 not supported");
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return;
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}
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@ -1,465 +0,0 @@
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/** @file
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Default exception handler
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/PrintLib.h>
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#include <Library/ArmDisassemblerLib.h>
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CHAR8 *gCondition[] = {
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"EQ",
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"NE",
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"CS",
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"CC",
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"MI",
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"PL",
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"VS",
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"VC",
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"HI",
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"LS",
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"GE",
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"LT",
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"GT",
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"LE",
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"",
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"2"
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};
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#define COND(_a) gCondition[((_a) >> 28)]
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CHAR8 *gReg[] = {
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"r0",
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"r1",
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"r2",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"sp",
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"lr",
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"pc"
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};
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CHAR8 *gLdmAdr[] = {
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"DA",
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"IA",
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"DB",
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"IB"
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};
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CHAR8 *gLdmStack[] = {
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"FA",
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"FD",
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"EA",
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"ED"
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};
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#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
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#define SIGN(_U) ((_U) ? "" : "-")
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#define WRITE(_Write) ((_Write) ? "!" : "")
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#define BYTE(_B) ((_B) ? "B":"")
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#define USER(_B) ((_B) ? "^" : "")
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CHAR8 mMregListStr[4*15 + 1];
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CHAR8 *
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MRegList (
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UINT32 OpCode
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)
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{
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UINTN Index, Start, End;
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BOOLEAN First;
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mMregListStr[0] = '\0';
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");
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for (Index = 0, First = TRUE; Index <= 15; Index++) {
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if ((OpCode & (1 << Index)) != 0) {
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Start = End = Index;
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for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {
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End = Index;
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}
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if (!First) {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, ",");
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} else {
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First = FALSE;
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}
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if (Start == End) {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]);
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, ", ");
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} else {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]);
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "-");
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[End]);
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}
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}
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}
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if (First) {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");
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}
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");
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// BugBug: Make caller pass in buffer it is cleaner
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return mMregListStr;
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}
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CHAR8 *
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FieldMask (
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IN UINT32 Mask
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)
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{
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return "";
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}
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UINT32
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RotateRight (
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IN UINT32 Op,
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IN UINT32 Shift
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)
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{
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return (Op >> Shift) | (Op << (32 - Shift));
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}
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/**
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Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instruction.
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We cheat and only decode instructions that access
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memory. If the instruction is not found we dump the instruction in hex.
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@param OpCodePtr Pointer to pointer of ARM instruction to disassemble.
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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@param Extended TRUE dump hex for instruction too.
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**/
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VOID
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DisassembleArmInstruction (
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IN UINT32 **OpCodePtr,
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OUT CHAR8 *Buf,
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OUT UINTN Size,
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IN BOOLEAN Extended
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)
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{
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UINT32 OpCode;
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CHAR8 *Type;
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CHAR8 *Root;
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BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
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UINT32 Rn, Rd, Rm;
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UINT32 IMod, Offset8, Offset12;
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UINT32 Index;
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UINT32 ShiftImm, Shift;
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OpCode = **OpCodePtr;
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Imm = (OpCode & BIT25) == BIT25; // I
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Pre = (OpCode & BIT24) == BIT24; // P
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Up = (OpCode & BIT23) == BIT23; // U
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WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
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Write = (OpCode & BIT21) == BIT21; // W
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Load = (OpCode & BIT20) == BIT20; // L
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Sign = (OpCode & BIT6) == BIT6; // S
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Half = (OpCode & BIT5) == BIT5; // H
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Rn = (OpCode >> 16) & 0xf;
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Rd = (OpCode >> 12) & 0xf;
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Rm = (OpCode & 0xf);
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if (Extended) {
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Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);
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Buf += Index;
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Size -= Index;
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}
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// LDREX, STREX
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if ((OpCode & 0x0fe000f0) == 0x01800090) {
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if (Load) {
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// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
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AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
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} else {
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// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
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AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
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}
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return;
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}
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// LDM/STM
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if ((OpCode & 0x0e000000) == 0x08000000) {
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if (Load) {
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// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
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// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
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// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
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AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
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} else {
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// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
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// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
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AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
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}
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return;
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}
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// LDR/STR Address Mode 2
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if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {
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Offset12 = OpCode & 0xfff;
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if ((OpCode & 0xfd70f000) == 0xf550f000) {
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Index = AsciiSPrint (Buf, Size, "PLD");
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} else {
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Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);
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}
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if (Pre) {
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if (!Imm) {
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// A5.2.2 [<Rn>, #+/-<offset_12>]
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// A5.2.5 [<Rn>, #+/-<offset_12>]
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));
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} else if ((OpCode & 0x03000ff0) == 0x03000000) {
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// A5.2.3 [<Rn>, +/-<Rm>]
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// A5.2.6 [<Rn>, +/-<Rm>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));
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} else {
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// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
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// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
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ShiftImm = (OpCode >> 7) & 0x1f;
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Shift = (OpCode >> 5) & 0x3;
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if (Shift == 0x0) {
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Type = "LSL";
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} else if (Shift == 0x1) {
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Type = "LSR";
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if (ShiftImm == 0) {
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ShiftImm = 32;
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}
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} else if (Shift == 0x2) {
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Type = "ASR";
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} else if (ShiftImm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
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return;
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} else {
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Type = "ROR";
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}
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
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}
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} else {
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// !Pre
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if (!Imm) {
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// A5.2.8 [<Rn>], #+/-<offset_12>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
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} else if ((OpCode & 0x03000ff0) == 0x03000000) {
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// A5.2.9 [<Rn>], +/-<Rm>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
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} else {
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// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
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ShiftImm = (OpCode >> 7) & 0x1f;
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Shift = (OpCode >> 5) & 0x3;
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if (Shift == 0x0) {
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Type = "LSL";
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} else if (Shift == 0x1) {
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Type = "LSR";
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if (ShiftImm == 0) {
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ShiftImm = 32;
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}
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} else if (Shift == 0x2) {
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Type = "ASR";
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} else if (ShiftImm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);
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// FIx me
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return;
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} else {
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Type = "ROR";
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}
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
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}
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}
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return;
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}
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if ((OpCode & 0x0e000000) == 0x00000000) {
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// LDR/STR address mode 3
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// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
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if (Load) {
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if (!Sign) {
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Root = "LDR%aH %a, ";
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} else if (!Half) {
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Root = "LDR%aSB %a, ";
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} else {
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Root = "LDR%aSH %a, ";
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}
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} else {
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if (!Sign) {
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Root = "STR%aH %a ";
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} else if (!Half) {
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Root = "LDR%aD %a ";
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} else {
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Root = "STR%aD %a ";
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}
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}
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Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
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Sign = (OpCode & BIT6) == BIT6;
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Half = (OpCode & BIT5) == BIT5;
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Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
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if (Pre & !Write) {
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// Immediate offset/index
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if (WriteBack) {
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// A5.3.2 [<Rn>, #+/-<offset_8>]
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// A5.3.4 [<Rn>, #+/-<offset_8>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
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} else {
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// A5.3.3 [<Rn>, +/-<Rm>]
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// A5.3.5 [<Rn>, +/-<Rm>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
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}
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} else {
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// Register offset/index
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if (WriteBack) {
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// A5.3.6 [<Rn>], #+/-<offset_8>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
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} else {
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// A5.3.7 [<Rn>], +/-<Rm>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
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}
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}
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return;
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}
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if ((OpCode & 0x0fb000f0) == 0x01000050) {
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// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
|
||||
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
|
||||
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
|
||||
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
|
||||
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0xfe500f00) == 0xf8100500) {
|
||||
// A4.1.59 RFE<addressing_mode> <Rn>{!}
|
||||
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0xfff000f0) == 0xe1200070) {
|
||||
// A4.1.7 BKPT <immed_16>
|
||||
AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0xfff10020) == 0xf1000000) {
|
||||
// A4.1.16 CPS<effect> <iflags> {, #<mode>}
|
||||
if (((OpCode >> 6) & 0x7) == 0) {
|
||||
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
|
||||
} else {
|
||||
IMod = (OpCode >> 18) & 0x3;
|
||||
Index = AsciiSPrint (
|
||||
Buf,
|
||||
Size,
|
||||
"CPS%a %a%a%a",
|
||||
(IMod == 3) ? "ID" : "IE",
|
||||
((OpCode & BIT8) != 0) ? "A" : "",
|
||||
((OpCode & BIT7) != 0) ? "I" : "",
|
||||
((OpCode & BIT6) != 0) ? "F" : ""
|
||||
);
|
||||
if ((OpCode & BIT17) != 0) {
|
||||
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0f000000) == 0x0f000000) {
|
||||
// A4.1.107 SWI{<cond>} <immed_24>
|
||||
AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0fb00000) == 0x01000000) {
|
||||
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
|
||||
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0db00000) == 0x01200000) {
|
||||
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
|
||||
if (Imm) {
|
||||
// MSR{<cond>} CPSR_<fields>, #<immediate>
|
||||
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
|
||||
} else {
|
||||
// MSR{<cond>} CPSR_<fields>, <Rm>
|
||||
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0xff000010) == 0xfe000000) {
|
||||
// A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
|
||||
AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0e000000) == 0x0c000000) {
|
||||
// A4.1.19 LDC and A4.1.96 SDC
|
||||
if ((OpCode & 0xf0000000) == 0xf0000000) {
|
||||
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);
|
||||
} else {
|
||||
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
|
||||
}
|
||||
|
||||
if (!Pre) {
|
||||
if (!Write) {
|
||||
// A5.5.5.5 [<Rn>], <option>
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
|
||||
} else {
|
||||
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
|
||||
}
|
||||
} else {
|
||||
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
|
||||
}
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0f000010) == 0x0e000010) {
|
||||
// A4.1.32 MRC2, MCR2
|
||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0ff00000) == 0x0c400000) {
|
||||
// A4.1.33 MRRC2, MCRR2
|
||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
|
||||
return;
|
||||
}
|
||||
|
||||
AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);
|
||||
|
||||
*OpCodePtr += 1;
|
||||
return;
|
||||
}
|
||||
@ -1,35 +0,0 @@
|
||||
#/** @file
|
||||
# ARM Disassembler library
|
||||
#
|
||||
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmDisassemblerLib
|
||||
FILE_GUID = 7ACEC173-F15D-426C-8F2F-BD86B4183EF1
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmDisassemblerLib
|
||||
|
||||
|
||||
[Sources.ARM]
|
||||
ArmDisassembler.c
|
||||
ThumbDisassembler.c
|
||||
|
||||
[Sources.AARCH64]
|
||||
Aarch64Disassembler.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
PrintLib
|
||||
DebugLib
|
||||
PeCoffGetEntryPointLib
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user