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MdeModulePkg: The patch eliminates two assumptions 

1) XHCI host controller hw always provides more than 5 interrupters.
Now using interrupter 0 to accommodate all received events.
2) XHCI host controller hw always provides 32bytes context size.
Now it dynamically detect context size and construct it.

also solved several issues:
1) Divides 64byte width register access to two 32bit registers access because some XHCI chipsets cannot support a single 64bit access.
2) Remove halt host controller statement in UsbBusDriverBindingStop(). It has been done by host controller’s DriverBindingStop(). And XhciDriverBindingStop() need XHCI host controller is in running state because it need execute DISABLE_SLOT cmd to release h/w resource.

signed-off-by: erictian
Reviewed-by: li-elvin

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12785 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
erictian 2011-11-25 08:08:54 +00:00
parent 4d6afad3b9
commit 6b4483cdbd
7 changed files with 1051 additions and 404 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

@ -721,7 +721,6 @@ XhcControlTransfer (
URB *Urb;
UINT8 Endpoint;
UINT8 Index;
UINT8 XhciDevAddr;
UINT8 DescriptorType;
UINT8 SlotId;
UINT8 TTT;
@ -793,11 +792,6 @@ XhcControlTransfer (
goto ON_EXIT;
}
//
// Acquire the actual device address assigned by XHCI's Address_Device cmd.
//
XhciDevAddr = Xhc->UsbDevContext[SlotId].XhciDevAddr;
//
// Hook the Set_Address request from UsbBus.
// According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.
@ -810,7 +804,7 @@ XhcControlTransfer (
//
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
(Xhc->UsbDevContext[Index + 1].SlotId == 0) &&
(Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value)) {
Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;
}
@ -850,7 +844,7 @@ XhcControlTransfer (
Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
Urb = XhcCreateUrb (
Xhc,
XhciDevAddr,
DeviceAddress,
Endpoint,
DeviceSpeed,
MaximumPacketLength,
@ -867,7 +861,7 @@ XhcControlTransfer (
Status = EFI_OUT_OF_RESOURCES;
goto ON_EXIT;
}
ASSERT (Urb->EvtRing == &Xhc->CtrlTrEventRing);
ASSERT (Urb->EvtRing == &Xhc->EventRing);
Status = XhcExecTransfer (Xhc, FALSE, Urb, Timeout);
//
@ -909,7 +903,11 @@ XhcControlTransfer (
MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
}
Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
} else {
Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
}
ASSERT_EFI_ERROR (Status);
} else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
ASSERT (Data != NULL);
@ -940,13 +938,12 @@ XhcControlTransfer (
MTT = 0;
}
Status = XhcConfigHubContext (
Xhc,
SlotId,
HubDesc->NumPorts,
TTT,
MTT
);
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcConfigHubContext (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);
} else {
Status = XhcConfigHubContext64 (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);
}
ASSERT_EFI_ERROR (Status);
}
} else if ((Request->Request == USB_REQ_SET_CONFIG) &&
(Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
@ -955,7 +952,12 @@ XhcControlTransfer (
//
for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
if (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->ConfigurationValue == (UINT8)Request->Value) {
XhcSetConfigCmd (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcSetConfigCmd (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
} else {
Status = XhcSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
ASSERT_EFI_ERROR (Status);
break;
}
}
@ -1073,7 +1075,6 @@ XhcBulkTransfer (
{
USB_XHCI_INSTANCE *Xhc;
URB *Urb;
UINT8 XhciDevAddr;
UINT8 SlotId;
EFI_STATUS Status;
EFI_STATUS RecoveryStatus;
@ -1118,18 +1119,13 @@ XhcBulkTransfer (
goto ON_EXIT;
}
//
// Acquire the actual device address assigned by XHCI's Address_Device cmd.
//
XhciDevAddr = Xhc->UsbDevContext[SlotId].XhciDevAddr;
//
// Create a new URB, insert it into the asynchronous
// schedule list, then poll the execution status.
//
Urb = XhcCreateUrb (
Xhc,
XhciDevAddr,
DeviceAddress,
EndPointAddress,
DeviceSpeed,
MaximumPacketLength,
@ -1147,7 +1143,7 @@ XhcBulkTransfer (
goto ON_EXIT;
}
ASSERT (Urb->EvtRing == &Xhc->BulkTrEventRing);
ASSERT (Urb->EvtRing == &Xhc->EventRing);
Status = XhcExecTransfer (Xhc, FALSE, Urb, Timeout);
@ -1223,7 +1219,6 @@ XhcAsyncInterruptTransfer (
USB_XHCI_INSTANCE *Xhc;
URB *Urb;
EFI_STATUS Status;
UINT8 XhciDevAddr;
UINT8 SlotId;
UINT8 Index;
UINT8 *Data;
@ -1262,8 +1257,7 @@ XhcAsyncInterruptTransfer (
// The delete request may happen after device is detached.
//
for (Index = 0; Index < 255; Index++) {
if ((Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
(Xhc->UsbDevContext[Index + 1].BusDevAddr == DeviceAddress)) {
if (Xhc->UsbDevContext[Index + 1].BusDevAddr == DeviceAddress) {
break;
}
}
@ -1273,12 +1267,7 @@ XhcAsyncInterruptTransfer (
goto ON_EXIT;
}
//
// Acquire the actual device address assigned by XHCI's Address_Device cmd.
//
XhciDevAddr = Xhc->UsbDevContext[Index + 1].XhciDevAddr;
Status = XhciDelAsyncIntTransfer (Xhc, XhciDevAddr, EndPointAddress);
Status = XhciDelAsyncIntTransfer (Xhc, DeviceAddress, EndPointAddress);
DEBUG ((EFI_D_INFO, "XhcAsyncInterruptTransfer: remove old transfer, Status = %r\n", Status));
goto ON_EXIT;
}
@ -1299,11 +1288,6 @@ XhcAsyncInterruptTransfer (
goto ON_EXIT;
}
//
// Acquire the actual device address assigned by XHCI's Address_Device cmd.
//
XhciDevAddr = Xhc->UsbDevContext[SlotId].XhciDevAddr;
Data = AllocateZeroPool (DataLength);
if (Data == NULL) {
@ -1314,7 +1298,7 @@ XhcAsyncInterruptTransfer (
Urb = XhcCreateUrb (
Xhc,
XhciDevAddr,
DeviceAddress,
EndPointAddress,
DeviceSpeed,
MaximumPacketLength,
@ -1333,7 +1317,7 @@ XhcAsyncInterruptTransfer (
goto ON_EXIT;
}
ASSERT (Urb->EvtRing == &Xhc->AsynIntTrEventRing);
ASSERT (Urb->EvtRing == &Xhc->EventRing);
InsertHeadList (&Xhc->AsyncIntTransfers, &Urb->UrbList);
//
@ -1393,7 +1377,6 @@ XhcSyncInterruptTransfer (
{
USB_XHCI_INSTANCE *Xhc;
URB *Urb;
UINT8 XhciDevAddr;
UINT8 SlotId;
EFI_STATUS Status;
EFI_STATUS RecoveryStatus;
@ -1441,14 +1424,9 @@ XhcSyncInterruptTransfer (
goto ON_EXIT;
}
//
// Acquire the actual device address assigned by XHCI's Address_Device cmd.
//
XhciDevAddr = Xhc->UsbDevContext[SlotId].XhciDevAddr;
Urb = XhcCreateUrb (
Xhc,
XhciDevAddr,
DeviceAddress,
EndPointAddress,
DeviceSpeed,
MaximumPacketLength,
@ -2072,8 +2050,11 @@ XhcDriverBindingStop (
(Xhc->UsbDevContext[Index + 1].SlotId == 0)) {
continue;
}
XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
if (Xhc->HcCParams.Data.Csz == 0) {
XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
} else {
XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
}
}
XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
@ -2108,11 +2089,11 @@ XhcDriverBindingStop (
// Restore original PCI attributes
//
PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationSet,
Xhc->OriginalPciAttributes,
NULL
);
PciIo,
EfiPciIoAttributeOperationSet,
Xhc->OriginalPciAttributes,
NULL
);
gBS->CloseProtocol (
Controller,

22
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
View File

@ -93,7 +93,7 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0xFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(Xhc, Offset, Bit) \
@ -228,25 +228,9 @@ struct _USB_XHCI_INSTANCE {
//
TRANSFER_RING CmdRing;
//
// CmdEventRing
// EventRing
//
EVENT_RING CmdEventRing;
//
// ControlTREventRing
//
EVENT_RING CtrlTrEventRing;
//
// BulkTREventRing
//
EVENT_RING BulkTrEventRing;
//
// IntTREventRing
//
EVENT_RING IntTrEventRing;
//
// AsyncIntTREventRing
//
EVENT_RING AsynIntTrEventRing;
EVENT_RING EventRing;
//
// Misc
//

103
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
View File

@ -191,39 +191,6 @@ XhcWriteOpReg16 (
}
}
/**
Write the data to the 8-bytes width XHCI operational register.
@param Xhc The XHCI Instance.
@param Offset The offset of the 8-bytes width operational register.
@param Data The data to write.
**/
VOID
XhcWriteOpReg64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT64 Data
)
{
EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
Status = Xhc->PciIo->Mem.Write (
Xhc->PciIo,
EfiPciIoWidthUint64,
XHC_BAR_INDEX,
(UINT64) (Xhc->CapLength + Offset),
1,
&Data
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteOpReg64: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
/**
Read XHCI door bell register.
@ -331,43 +298,6 @@ XhcReadRuntimeReg (
return Data;
}
/**
Read 8-bytes width XHCI runtime register.
@param Xhc The XHCI Instance.
@param Offset The offset of the 8-bytes width runtime register.
@return The register content read
**/
UINT64
XhcReadRuntimeReg64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
)
{
UINT64 Data;
EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint64,
XHC_BAR_INDEX,
(UINT64) (Xhc->RTSOff + Offset),
1,
&Data
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg64: Pci Io Read error - %r at %d\n", Status, Offset));
Data = 0xFFFFFFFFFFFFFFFFULL;
}
return Data;
}
/**
Write the data to the XHCI runtime register.
@ -401,39 +331,6 @@ XhcWriteRuntimeReg (
}
}
/**
Write the data to the 8-bytes width XHCI runtime register.
@param Xhc The XHCI Instance.
@param Offset The offset of the 8-bytes width runtime register.
@param Data The data to write.
**/
VOID
XhcWriteRuntimeReg64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT64 Data
)
{
EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
Status = Xhc->PciIo->Mem.Write (
Xhc->PciIo,
EfiPciIoWidthUint64,
XHC_BAR_INDEX,
(UINT64) (Xhc->RTSOff + Offset),
1,
&Data
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg64: Pci Io Write error: %r at %d\n", Status, Offset));
}
}
/**
Read XHCI extended capability register.

45
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
View File

@ -265,21 +265,6 @@ XhcWriteOpReg16 (
IN UINT16 Data
);
/**
Write the data to the 8-bytes width XHCI operational register.
@param Xhc The XHCI Instance.
@param Offset The offset of the 8-bytes width operational register.
@param Data The data to write.
**/
VOID
XhcWriteOpReg64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT64 Data
);
/**
Read XHCI runtime register.
@ -295,21 +280,6 @@ XhcReadRuntimeReg (
IN UINT32 Offset
);
/**
Read 8-bytes width XHCI runtime register.
@param Xhc The XHCI Instance.
@param Offset The offset of the 8-bytes width runtime register.
@return The register content read
**/
UINT64
XhcReadRuntimeReg64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
Write the data to the XHCI runtime register.
@ -325,21 +295,6 @@ XhcWriteRuntimeReg (
IN UINT32 Data
);
/**
Write the data to the 8-bytes width XHCI runtime register.
@param Xhc The XHCI Instance.
@param Offset The offset of the 8-bytes width runtime register.
@param Data The data to write.
**/
VOID
XhcWriteRuntimeReg64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset,
IN UINT64 Data
);
/**
Read XHCI door bell register.

946
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

File diff suppressed because it is too large Load Diff

245
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
View File

@ -111,6 +111,12 @@ typedef union _USB_DEV_ROUTE {
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
//
// Store logical device address assigned by UsbBus
// It's because some XHCI host controllers may assign the same physcial device
// address for those devices inserted at different root port.
//
UINT8 BusAddr;
UINT8 DevAddr;
UINT8 EpAddr;
EFI_USB_DATA_DIRECTION Direction;
@ -144,7 +150,6 @@ typedef struct _TRANSFER_RING {
} TRANSFER_RING;
typedef struct _EVENT_RING {
UINT32 EventInterrupter;
VOID *ERSTBase;
VOID *EventRingSeg0;
UINTN TrbNumber;
@ -577,6 +582,46 @@ typedef struct _SLOT_CONTEXT {
UINT32 RsvdZ7;
} SLOT_CONTEXT;
typedef struct _SLOT_CONTEXT_64 {
UINT32 RouteString:20;
UINT32 Speed:4;
UINT32 RsvdZ1:1;
UINT32 MTT:1;
UINT32 Hub:1;
UINT32 ContextEntries:5;
UINT32 MaxExitLatency:16;
UINT32 RootHubPortNum:8;
UINT32 PortNum:8;
UINT32 TTHubSlotId:8;
UINT32 TTPortNum:8;
UINT32 TTT:2;
UINT32 RsvdZ2:4;
UINT32 InterTarget:10;
UINT32 DeviceAddress:8;
UINT32 RsvdZ3:19;
UINT32 SlotState:5;
UINT32 RsvdZ4;
UINT32 RsvdZ5;
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
UINT32 RsvdZ15;
} SLOT_CONTEXT_64;
//
// 6.2.3 Endpoint Context
//
@ -609,6 +654,47 @@ typedef struct _ENDPOINT_CONTEXT {
UINT32 RsvdZ7;
} ENDPOINT_CONTEXT;
typedef struct _ENDPOINT_CONTEXT_64 {
UINT32 EPState:3;
UINT32 RsvdZ1:5;
UINT32 Mult:2;
UINT32 MaxPStreams:5;
UINT32 LSA:1;
UINT32 Interval:8;
UINT32 RsvdZ2:8;
UINT32 RsvdZ3:1;
UINT32 CErr:2;
UINT32 EPType:3;
UINT32 RsvdZ4:1;
UINT32 HID:1;
UINT32 MaxBurstSize:8;
UINT32 MaxPacketSize:16;
UINT32 PtrLo;
UINT32 PtrHi;
UINT32 AverageTRBLength:16;
UINT32 MaxESITPayload:16;
UINT32 RsvdZ5;
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
UINT32 RsvdZ15;
} ENDPOINT_CONTEXT_64;
//
// 6.2.5.1 Input Control Context
//
@ -623,6 +709,25 @@ typedef struct _INPUT_CONTRL_CONTEXT {
UINT32 RsvdZ6;
} INPUT_CONTRL_CONTEXT;
typedef struct _INPUT_CONTRL_CONTEXT_64 {
UINT32 Dword1;
UINT32 Dword2;
UINT32 RsvdZ1;
UINT32 RsvdZ2;
UINT32 RsvdZ3;
UINT32 RsvdZ4;
UINT32 RsvdZ5;
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
} INPUT_CONTRL_CONTEXT_64;
//
// 6.2.1 Device Context
//
@ -631,6 +736,11 @@ typedef struct _DEVICE_CONTEXT {
ENDPOINT_CONTEXT EP[31];
} DEVICE_CONTEXT;
typedef struct _DEVICE_CONTEXT_64 {
SLOT_CONTEXT_64 Slot;
ENDPOINT_CONTEXT_64 EP[31];
} DEVICE_CONTEXT_64;
//
// 6.2.5 Input Context
//
@ -640,6 +750,13 @@ typedef struct _INPUT_CONTEXT {
ENDPOINT_CONTEXT EP[31];
} INPUT_CONTEXT;
typedef struct _INPUT_CONTEXT_64 {
INPUT_CONTRL_CONTEXT_64 InputControlContext;
SLOT_CONTEXT_64 Slot;
ENDPOINT_CONTEXT_64 EP[31];
} INPUT_CONTEXT_64;
/**
Initialize the XHCI host controller for schedule.
@ -703,7 +820,7 @@ XhcExecTransfer (
the device and endpoint.
@param Xhc The XHCI Instance.
@param DevAddr The address of the target device.
@param BusAddr The logical device address assigned by UsbBus driver.
@param EpNum The endpoint of the target.
@retval EFI_SUCCESS An asynchronous transfer is removed.
@ -713,7 +830,7 @@ XhcExecTransfer (
EFI_STATUS
XhciDelAsyncIntTransfer (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 DevAddr,
IN UINT8 BusAddr,
IN UINT8 EpNum
);
@ -750,21 +867,6 @@ XhcClearBiosOwnership (
IN USB_XHCI_INSTANCE *Xhc
);
/**
Find out the slot id according to device address assigned by XHCI's Address_Device cmd.
@param Xhc The XHCI Instance.
@param DevAddr The device address of the target device.
@return The slot id used by the device.
**/
UINT8
XhcDevAddrToSlotId (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 DevAddr
);
/**
Find out the slot id according to the device's route string.
@ -870,6 +972,29 @@ XhcConfigHubContext (
IN UINT8 MTT
);
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@param Xhc The XHCI Instance.
@param SlotId The slot id to be configured.
@param PortNum The total number of downstream port supported by the hub.
@param TTT The TT think time of the hub device.
@param MTT The multi-TT of the hub device.
@retval EFI_SUCCESS Successfully configure the hub device's slot context.
**/
EFI_STATUS
XhcConfigHubContext64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 SlotId,
IN UINT8 PortNum,
IN UINT8 TTT,
IN UINT8 MTT
);
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@ -890,6 +1015,28 @@ XhcSetConfigCmd (
IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@param Xhc The XHCI Instance.
@param SlotId The slot id to be configured.
@param DeviceSpeed The device's speed.
@param ConfigDesc The pointer to the usb device configuration descriptor.
@retval EFI_SUCCESS Successfully configure all the device endpoints.
**/
EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 SlotId,
IN UINT8 DeviceSpeed,
IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
Find out the actual device address according to the requested device address from UsbBus.
@ -928,6 +1075,28 @@ XhcInitializeDeviceSlot (
IN UINT8 DeviceSpeed
);
/**
Assign and initialize the device slot for a new device.
@param Xhc The XHCI Instance.
@param ParentRouteChart The route string pointed to the parent device.
@param ParentPort The port at which the device is located.
@param RouteChart The route string pointed to the device.
@param DeviceSpeed The device speed.
@retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
**/
EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
IN USB_XHCI_INSTANCE *Xhc,
IN USB_DEV_ROUTE ParentRouteChart,
IN UINT16 ParentPort,
IN USB_DEV_ROUTE RouteChart,
IN UINT8 DeviceSpeed
);
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@ -946,6 +1115,26 @@ XhcEvaluateContext (
IN UINT32 MaxPacketSize
);
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@param Xhc The XHCI Instance.
@param SlotId The slot id to be evaluated.
@param MaxPacketSize The max packet size supported by the device control transfer.
@retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
**/
EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 SlotId,
IN UINT32 MaxPacketSize
);
/**
Disable the specified device slot.
@ -962,6 +1151,24 @@ XhcDisableSlotCmd (
IN UINT8 SlotId
);
/**
Disable the specified device slot.
@param Xhc The XHCI Instance.
@param SlotId The slot id to be disabled.
@retval EFI_SUCCESS Successfully disable the device slot.
**/
EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 SlotId
);
/**
Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
@ -1032,14 +1239,12 @@ CreateTransferRing (
Create XHCI event ring.
@param Xhc The XHCI Instance.
@param EventInterrupter The interrupter of event.
@param EventRing The created event ring.
**/
VOID
CreateEventRing (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 EventInterrupter,
OUT EVENT_RING *EventRing
);

1
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c
View File

@ -1431,7 +1431,6 @@ UsbBusControllerDriverStop (
// BugBug: Raise TPL to callback level instead of USB_BUS_TPL to avoid TPL conflict
//
OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
UsbHcSetState (Bus, EfiUsbHcStateHalt);
RootHub = Bus->Devices[0];
RootIf = RootHub->Interfaces[0];