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MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress in AsmFlushCacheLine() 

The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly 
implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register.
The EBX register value is saved onto the stack before CPUID and restored from the stack 
after CPUID.

The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the 
LinearAddress parameter value on the stack.  The hardcoded lookup using [esp + 4] is not correct.
Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent
this issue from occurring again if there are changes to the inline assembly in the future.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney 2015-04-30 07:25:07 +00:00 committed by erictian
parent 2bbe9553c4
commit 6f7878a972
2 changed files with 3 additions and 1 deletions
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2
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm
View File

@ -39,7 +39,9 @@ AsmFlushCacheLine PROC
; then promote flush range to flush entire cache. ; then promote flush range to flush entire cache.
; ;
mov eax, 1 mov eax, 1
push ebx
cpuid cpuid
pop ebx
mov eax, [esp + 4] mov eax, [esp + 4]
test edx, BIT19 test edx, BIT19
jz @F jz @F

2
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
View File

@ -45,7 +45,7 @@ AsmFlushCacheLine (
cpuid cpuid
test edx, BIT19 test edx, BIT19
jz NoClflush jz NoClflush
mov eax, [esp + 4] mov eax, dword ptr [LinearAddress]
clflush [eax] clflush [eax]
jmp Done jmp Done
NoClflush: NoClflush: