MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress in AsmFlushCacheLine()

The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly 
implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register.
The EBX register value is saved onto the stack before CPUID and restored from the stack 
after CPUID.

The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the 
LinearAddress parameter value on the stack.  The hardcoded lookup using [esp + 4] is not correct.
Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent
this issue from occurring again if there are changes to the inline assembly in the future.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524

MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm

@@ -39,7 +39,9 @@ AsmFlushCacheLine   PROC
     ; then promote flush range to flush entire cache.
     ;
     mov     eax, 1
+    push    ebx
     cpuid
+    pop     ebx
     mov     eax, [esp + 4]
     test    edx, BIT19
     jz      @F

MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c

@@ -45,7 +45,7 @@ AsmFlushCacheLine (
     cpuid
     test    edx, BIT19
     jz      NoClflush
-    mov     eax, [esp + 4]
+    mov     eax, dword ptr [LinearAddress]
     clflush [eax]
     jmp     Done
 NoClflush: