mirror of https://github.com/acidanthera/audk.git
OvmfPkg/ResetVector: Depend on PCD values of the page tables.
Currently, the value of the page tables' address is hard-coded in the ResetVector. This patch replaces these values with a PCD dependency. A check for the size has been added to alert the developer to rewrite the ASM according to the new size, if it has been changed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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@ -44,10 +44,11 @@ BITS 32
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SetCr3ForPageTables64:
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;
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; For OVMF, build some initial page tables at 0x800000-0x806000.
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; For OVMF, build some initial page tables at
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; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
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;
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; This range should match with PcdOvmfSecPageTablesBase and
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; PcdOvmfSecPageTablesSize which are declared in the FDF files.
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; This range should match with PcdOvmfSecPageTablesSize which is
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; declared in the FDF files.
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;
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; At the end of PEI, the pages tables will be rebuilt into a
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; more permanent location by DxeIpl.
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@ -56,21 +57,21 @@ SetCr3ForPageTables64:
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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clearPageTablesMemoryLoop:
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mov dword[ecx * 4 + 0x800000 - 4], eax
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mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
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loop clearPageTablesMemoryLoop
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[0x800000], 0x801000 + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[0x801000], 0x802000 + PAGE_PDP_ATTR
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mov dword[0x801008], 0x803000 + PAGE_PDP_ATTR
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mov dword[0x801010], 0x804000 + PAGE_PDP_ATTR
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mov dword[0x801018], 0x805000 + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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@ -81,13 +82,13 @@ pageTableEntriesLoop:
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dec eax
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shl eax, 21
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add eax, PAGE_2M_PDE_ATTR
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mov [ecx * 8 + 0x802000 - 8], eax
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mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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loop pageTableEntriesLoop
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;
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; Set CR3 now that the paging structures are available
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;
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mov eax, 0x800000
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mov eax, PT_ADDR (0)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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@ -29,9 +29,14 @@
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ResetVector.nasmb
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[Packages]
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OvmfPkg/OvmfPkg.dec
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MdePkg/MdePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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[BuildOptions]
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*_*_IA32_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/
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*_*_X64_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/
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[Pcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize
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@ -53,6 +53,13 @@
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%include "Ia32/SearchForSecEntry.asm"
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%ifdef ARCH_X64
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#include <AutoGen.h>
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%if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)
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%error "This implementation inherently depends on PcdOvmfSecPageTablesSize"
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%endif
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%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))
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%include "Ia32/Flat32ToFlat64.asm"
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%include "Ia32/PageTables64.asm"
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%endif
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