mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseLib: BaseLib for RISCV64 architecture
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
This commit is contained in:
Abner Chang
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@ -5,6 +5,8 @@
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) Microsoft Corporation.<BR>
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Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -125,6 +127,30 @@ typedef struct {
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#endif // defined (MDE_CPU_AARCH64)
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#if defined (MDE_CPU_RISCV64)
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///
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/// The RISC-V architecture context buffer used by SetJump() and LongJump().
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///
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typedef struct {
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UINT64 RA;
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UINT64 S0;
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UINT64 S1;
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UINT64 S2;
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UINT64 S3;
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UINT64 S4;
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UINT64 S5;
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UINT64 S6;
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UINT64 S7;
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UINT64 S8;
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UINT64 S9;
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UINT64 S10;
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UINT64 S11;
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UINT64 SP;
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} BASE_LIBRARY_JUMP_BUFFER;
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#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
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#endif // defined (MDE_CPU_RISCV64)
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//
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// String Services
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@ -4,6 +4,7 @@
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# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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@ -20,7 +21,7 @@
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LIBRARY_CLASS = BaseLib
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#
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# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
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# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
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#
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[Sources]
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@ -381,6 +382,21 @@
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AArch64/CpuBreakpoint.asm | MSFT
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AArch64/SpeculationBarrier.asm | MSFT
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[Sources.RISCV64]
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Math64.c
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Unaligned.c
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RiscV64/InternalSwitchStack.c
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RiscV64/CpuBreakpoint.c
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RiscV64/GetInterruptState.c
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RiscV64/DisableInterrupts.c
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RiscV64/EnableInterrupts.c
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RiscV64/CpuPause.c
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RiscV64/RiscVSetJumpLongJump.S | GCC
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RiscV64/RiscVCpuBreakpoint.S | GCC
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RiscV64/RiscVCpuPause.S | GCC
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RiscV64/RiscVInterrupt.S | GCC
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RiscV64/FlushCache.S | GCC
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[Packages]
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MdePkg/MdePkg.dec
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@ -0,0 +1,27 @@
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/** @file
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CPU breakpoint for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern VOID RiscVCpuBreakpoint (VOID);
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/**
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Generates a breakpoint on the CPU.
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Generates a breakpoint on the CPU. The breakpoint must be implemented such
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that code can resume normal execution after the breakpoint.
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**/
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VOID
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EFIAPI
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CpuBreakpoint (
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VOID
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)
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{
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RiscVCpuBreakpoint ();
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}
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@ -0,0 +1,29 @@
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/** @file
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CPU pause for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern VOID RiscVCpuPause (VOID);
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/**
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Requests CPU to pause for a short period of time.
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Requests CPU to pause for a short period of time. Typically used in MP
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systems to prevent memory starvation while waiting for a spin lock.
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**/
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VOID
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EFIAPI
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CpuPause (
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VOID
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)
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{
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RiscVCpuPause ();
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}
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@ -0,0 +1,24 @@
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/** @file
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CPU disable interrupt function for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
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/**
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Disables CPU interrupts.
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**/
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VOID
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EFIAPI
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DisableInterrupts (
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VOID
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)
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{
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RiscVDisableSupervisorModeInterrupts ();
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}
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@ -0,0 +1,25 @@
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/** @file
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CPU enable interrupt function for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
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/**
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Enables CPU interrupts.
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**/
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VOID
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EFIAPI
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EnableInterrupts (
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VOID
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)
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{
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RiscVEnableSupervisorModeInterrupt ();
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}
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@ -0,0 +1,21 @@
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//------------------------------------------------------------------------------
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//
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// RISC-V cache operation.
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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.align 3
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ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
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ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
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ASM_PFX(RiscVInvalidateInstCacheAsm):
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fence.i
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ret
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ASM_PFX(RiscVInvalidateDataCacheAsm):
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fence
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ret
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@ -0,0 +1,35 @@
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/** @file
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CPU get interrupt state function for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
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/**
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Retrieves the current CPU interrupt state.
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Returns TRUE is interrupts are currently enabled. Otherwise
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returns FALSE.
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@retval TRUE CPU interrupts are enabled.
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@retval FALSE CPU interrupts are disabled.
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**/
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BOOLEAN
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EFIAPI
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GetInterruptState (
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VOID
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)
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{
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unsigned long RetValue;
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RetValue = RiscVGetSupervisorModeInterrupts ();
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return RetValue? TRUE: FALSE;
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}
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@ -0,0 +1,55 @@
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/** @file
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Switch stack function for RISC-V
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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/**
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Transfers control to a function starting with a new stack.
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Transfers control to the function specified by EntryPoint using the
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new stack specified by NewStack and passing in the parameters specified
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by Context1 and Context2. Context1 and Context2 are optional and may
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be NULL. The function EntryPoint must never return.
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Marker will be ignored on IA-32, x64, and EBC.
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IPF CPUs expect one additional parameter of type VOID * that specifies
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the new backing store pointer.
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If EntryPoint is NULL, then ASSERT().
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If NewStack is NULL, then ASSERT().
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@param EntryPoint A pointer to function to call with the new stack.
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@param Context1 A pointer to the context to pass into the EntryPoint
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function.
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@param Context2 A pointer to the context to pass into the EntryPoint
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function.
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@param NewStack A pointer to the new stack to use for the EntryPoint
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function.
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@param Marker VA_LIST marker for the variable argument list.
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**/
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VOID
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EFIAPI
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InternalSwitchStack (
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IN SWITCH_STACK_ENTRY_POINT EntryPoint,
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IN VOID *Context1, OPTIONAL
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IN VOID *Context2, OPTIONAL
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IN VOID *NewStack,
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IN VA_LIST Marker
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)
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{
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BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
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DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \
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EntryPoint, Context1, Context2, NewStack));
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JumpBuffer.RA = (UINTN)EntryPoint;
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JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
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JumpBuffer.S0 = (UINT64)(UINTN)Context1;
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JumpBuffer.S1 = (UINT64)(UINTN)Context2;
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LongJump (&JumpBuffer, (UINTN)-1);
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ASSERT(FALSE);
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}
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//------------------------------------------------------------------------------
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//
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// CpuBreakpoint for RISC-V
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
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ASM_PFX(RiscVCpuBreakpoint):
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ebreak
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ret
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//------------------------------------------------------------------------------
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//
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// CpuPause for RISC-V
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(RiscVCpuPause)
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ASM_PFX(RiscVCpuPause):
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nop
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ret
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//------------------------------------------------------------------------------
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//
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// RISC-V Supervisor Mode interrupt enable/disable
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
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ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
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ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
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# define MSTATUS_SIE 0x00000002
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# define CSR_SSTATUS 0x100
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ASM_PFX(RiscVDisableSupervisorModeInterrupts):
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li a1, MSTATUS_SIE
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csrc CSR_SSTATUS, a1
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ret
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ASM_PFX(RiscVEnableSupervisorModeInterrupt):
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li a1, MSTATUS_SIE
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csrs CSR_SSTATUS, a1
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ret
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ASM_PFX(RiscVGetSupervisorModeInterrupts):
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csrr a0, CSR_SSTATUS
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andi a0, a0, MSTATUS_SIE
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ret
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@ -0,0 +1,55 @@
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//------------------------------------------------------------------------------
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//
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// Set/Long jump for RISC-V
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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# define REG_S sd
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# define REG_L ld
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# define SZREG 8
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.align 3
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.globl SetJump
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SetJump:
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REG_S ra, 0*SZREG(a0)
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REG_S s0, 1*SZREG(a0)
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REG_S s1, 2*SZREG(a0)
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REG_S s2, 3*SZREG(a0)
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REG_S s3, 4*SZREG(a0)
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REG_S s4, 5*SZREG(a0)
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REG_S s5, 6*SZREG(a0)
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REG_S s6, 7*SZREG(a0)
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REG_S s7, 8*SZREG(a0)
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REG_S s8, 9*SZREG(a0)
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REG_S s9, 10*SZREG(a0)
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REG_S s10, 11*SZREG(a0)
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REG_S s11, 12*SZREG(a0)
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REG_S sp, 13*SZREG(a0)
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li a0, 0
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ret
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.globl InternalLongJump
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InternalLongJump:
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REG_L ra, 0*SZREG(a0)
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REG_L s0, 1*SZREG(a0)
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REG_L s1, 2*SZREG(a0)
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REG_L s2, 3*SZREG(a0)
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REG_L s3, 4*SZREG(a0)
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REG_L s4, 5*SZREG(a0)
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REG_L s5, 6*SZREG(a0)
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REG_L s6, 7*SZREG(a0)
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REG_L s7, 8*SZREG(a0)
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REG_L s8, 9*SZREG(a0)
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REG_L s9, 10*SZREG(a0)
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REG_L s10, 11*SZREG(a0)
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REG_L s11, 12*SZREG(a0)
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REG_L sp, 13*SZREG(a0)
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add a0, s0, 0
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add a1, s1, 0
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add a2, s2, 0
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add a3, s3, 0
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ret
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