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CpuExceptionHandlerLib: Added a separate stack for timer.

This commit is contained in:
Mikhail Krichanov 2024-09-09 08:58:57 +03:00
parent 5515e17ae8
commit 76ac8a5fb0
3 changed files with 3 additions and 1 deletions
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2
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
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@ -40,7 +40,7 @@
#include "ArchInterruptDefs.h"
#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
(FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + 1)
#define CPU_STACK_SWITCH_EXCEPTION_LIST \
FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
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@ -226,6 +226,7 @@ ArchSetupExceptionStack (
StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
Tss->ESP0 = StackTop;
StackTop -= CPU_KNOWN_GOOD_STACK_SIZE;
Tss->SS0 = AsmReadSs ();
Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
//

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@ -234,6 +234,7 @@ ArchSetupExceptionStack (
StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
Tss->RSP0 = StackTop;
StackTop -= CPU_KNOWN_GOOD_STACK_SIZE;
Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
//
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;