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MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging

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5-level paging is documented in white paper:
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf

Commit f8113e25001e715390127f23e2197252cbd6d1a2
changed Cpuid.h already.

This patch updates IA32_CR4 structure to include LA57 field.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ray Ni 2019-06-12 11:04:52 +08:00
parent 7e56f8928d
commit 7c5010c7f8
1 changed files with 2 additions and 1 deletions
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MdePkg/Include/Library/BaseLib.h
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@ -5324,7 +5324,8 @@ typedef union {
UINT32 OSXMMEXCPT:1; ///< Operating System Support for
///< Unmasked SIMD Floating Point
///< Exceptions.
UINT32 Reserved_0:2; ///< Reserved.
UINT32 Reserved_2:1; ///< Reserved.
UINT32 LA57:1; ///< Linear Address 57bit.
UINT32 VMXE:1; ///< VMX Enable
UINT32 Reserved_1:18; ///< Reserved.
} Bits;