mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/Include: Add VMX MSR register structures
https://bugzilla.tianocore.org/show_bug.cgi?id=279 Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER structures with the bit fields for these two MSRs. Also add MSEG_HEADER structure whose base address is in the MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
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Michael Kinney
parent
f12367a0b1
commit
831d287a99
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@ -19,6 +19,14 @@
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.
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**/
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#ifndef __ARCHITECTURAL_MSR_H__
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@ -411,7 +419,7 @@ typedef union {
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/**
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SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =
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SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
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1.
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@param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
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@ -471,6 +479,25 @@ typedef union {
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UINT64 Uint64;
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} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
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/**
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MSEG header that is located at the physical address specified by the MsegBase
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field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
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**/
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typedef struct {
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UINT32 MsegHeaderRevision;
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UINT32 MonitorFeatures;
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UINT32 GdtrLimit;
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UINT32 GdtrBaseOffset;
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UINT32 CsSelector;
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UINT32 EipOffset;
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UINT32 EspOffset;
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UINT32 Cr3Offset;
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//
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// Pad header so total size is 2KB
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//
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UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
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} MSEG_HEADER;
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/**
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Base address of the logical processor's SMRAM image (RO, SMM only). If
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@ -3681,14 +3708,119 @@ typedef union {
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<b>Example usage</b>
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@code
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UINT64 Msr;
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MSR_IA32_VMX_BASIC_REGISTER Msr;
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Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
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Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
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@endcode
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@note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
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**/
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#define MSR_IA32_VMX_BASIC 0x00000480
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/**
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MSR information returned for MSR index #MSR_IA32_VMX_BASIC
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 30:0] VMCS revision identifier used by the processor. Processors
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/// that use the same VMCS revision identifier use the same size for VMCS
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/// regions (see subsequent item on bits 44:32).
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///
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/// @note Earlier versions of this manual specified that the VMCS revision
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/// identifier was a 32-bit field in bits 31:0 of this MSR. For all
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/// processors produced prior to this change, bit 31 of this MSR was read
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/// as 0.
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///
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UINT32 VmcsRevisonId:31;
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UINT32 MustBeZero:1;
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///
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/// [Bit 44:32] Reports the number of bytes that software should allocate
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/// for the VMXON region and any VMCS region. It is a value greater than
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/// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
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///
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UINT32 VmcsSize:13;
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UINT32 Reserved1:3;
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///
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/// [Bit 48] Indicates the width of the physical addresses that may be used
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/// for the VMXON region, each VMCS, and data structures referenced by
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/// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
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/// transitions). If the bit is 0, these addresses are limited to the
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/// processor's physical-address width. If the bit is 1, these addresses
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/// are limited to 32 bits. This bit is always 0 for processors that
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/// support Intel 64 architecture.
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///
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/// @note On processors that support Intel 64 architecture, the pointer
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/// must not set bits beyond the processor's physical address width.
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///
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UINT32 VmcsAddressWidth:1;
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///
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/// [Bit 49] If bit 49 is read as 1, the logical processor supports the
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/// dual-monitor treatment of system-management interrupts and
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/// system-management mode. See Section 34.15 for details of this treatment.
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///
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UINT32 DualMonitor:1;
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///
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/// [Bit 53:50] report the memory type that should be used for the VMCS,
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/// for data structures referenced by pointers in the VMCS (I/O bitmaps,
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/// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
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/// header. If software needs to access these data structures (e.g., to
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/// modify the contents of the MSR bitmaps), it can configure the paging
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/// structures to map them into the linear-address space. If it does so,
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/// it should establish mappings that use the memory type reported bits
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/// 53:50 in this MSR.
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///
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/// As of this writing, all processors that support VMX operation indicate
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/// the write-back type.
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///
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/// If software needs to access these data structures (e.g., to modify
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/// the contents of the MSR bitmaps), it can configure the paging
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/// structures to map them into the linear-address space. If it does so,
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/// it should establish mappings that use the memory type reported in this
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/// MSR.
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///
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/// @note Alternatively, software may map any of these regions or
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/// structures with the UC memory type. (This may be necessary for the MSEG
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/// header.) Doing so is discouraged unless necessary as it will cause the
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/// performance of software accesses to those structures to suffer.
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///
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///
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UINT32 MemoryType:4;
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///
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/// [Bit 54] If bit 54 is read as 1, the logical processor reports
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/// information in the VM-exit instruction-information field on VM exits
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/// due to execution of the INS and OUTS instructions. This reporting is
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/// done only if this bit is read as 1.
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///
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UINT32 InsOutsReporting:1;
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///
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/// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
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/// be cleared to 0. See Appendix A.2 for details. It also reports support
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/// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
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/// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
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/// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
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/// Appendix A.4, and Appendix A.5 for details.
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///
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UINT32 VmxControls:1;
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UINT32 Reserved2:8;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_IA32_VMX_BASIC_REGISTER;
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///
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/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
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///
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#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
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#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
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///
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/// @}
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///
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/**
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Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
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@ -3777,14 +3909,96 @@ typedef union {
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<b>Example usage</b>
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@code
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UINT64 Msr;
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IA32_VMX_MISC_REGISTER Msr;
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Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);
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Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
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@endcode
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@note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
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**/
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#define MSR_IA32_VMX_MISC 0x00000485
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/**
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MSR information returned for MSR index #IA32_VMX_MISC
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 4:0] Reports a value X that specifies the relationship between the
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/// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
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/// Specifically, the VMX-preemption timer (if it is active) counts down by
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/// 1 every time bit X in the TSC changes due to a TSC increment.
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///
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UINT32 VmxTimerRatio:5;
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///
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/// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
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/// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
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/// details. This bit is read as 1 on any logical processor that supports
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/// the 1-setting of the "unrestricted guest" VM-execution control.
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///
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UINT32 VmExitEferLma:1;
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///
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/// [Bit 6] reports (if set) the support for activity state 1 (HLT).
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///
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UINT32 HltActivityStateSupported:1;
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///
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/// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
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///
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UINT32 ShutdownActivityStateSupported:1;
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///
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/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
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///
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UINT32 WaitForSipiActivityStateSupported:1;
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UINT32 Reserved1:6;
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///
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/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
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/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
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/// See Section 34.15.6.4.
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///
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UINT32 SmBaseMsrSupported:1;
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///
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/// [Bits 24:16] Indicate the number of CR3-target values supported by the
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/// processor. This number is a value between 0 and 256, inclusive (bit 24
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/// is set if and only if bits 23:16 are clear).
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///
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UINT32 NumberOfCr3TargetValues:9;
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///
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/// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
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/// number of MSRs that should appear in the VM-exit MSR-store list, the
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/// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
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/// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
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/// recommended maximum number of MSRs to be included in each list. If the
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/// limit is exceeded, undefined processor behavior may result (including a
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/// machine check during the VMX transition).
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///
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UINT32 MsrStoreListMaximum:3;
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///
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/// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
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/// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
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/// (see Section 34.14.4).
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///
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UINT32 BlockSmiSupported:1;
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///
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/// [Bit 29] read as 1, software can use VMWRITE to write to any supported
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/// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
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/// information fields.
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///
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UINT32 VmWriteSupported:1;
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UINT32 Reserved2:2;
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///
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/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
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/// processor.
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///
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UINT32 MsegRevisionIdentifier:32;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} IA32_VMX_MISC_REGISTER;
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/**
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Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
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