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UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions 

https://bugzilla.tianocore.org/show_bug.cgi?id=277

Remove dependency on layout of PROCESSOR_SMM_DESCRIPTOR
everywhere possible.  The only exception is the standard
SMI entry handler template that is included with the
PiSmmCpuDxeSmm module.  This allows an instance of the
SmmCpuFeaturesLib to provide alternate
PROCESSOR_SMM_DESCRIPTOR structure layouts.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Michael Kinney 2016-11-28 14:13:24 -08:00
parent 26ab5ac362
commit f12367a0b1
8 changed files with 60 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
View File

@ -31,6 +31,9 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
.equ MSR_EFER, 0xc0000080
.equ MSR_EFER_XD, 0x800
#
# Constants relating to PROCESSOR_SMM_DESCRIPTOR
#
.equ DSC_OFFSET, 0xfb00
.equ DSC_GDTPTR, 0x30
.equ DSC_GDTSIZ, 0x38

3
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
View File

@ -26,6 +26,9 @@ MSR_IA32_MISC_ENABLE EQU 1A0h
MSR_EFER EQU 0c0000080h
MSR_EFER_XD EQU 0800h
;
; Constants relating to PROCESSOR_SMM_DESCRIPTOR
;
DSC_OFFSET EQU 0fb00h
DSC_GDTPTR EQU 30h
DSC_GDTSIZ EQU 38h

3
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
View File

@ -22,6 +22,9 @@
%define MSR_EFER 0xc0000080
%define MSR_EFER_XD 0x800
;
; Constants relating to PROCESSOR_SMM_DESCRIPTOR
;
%define DSC_OFFSET 0xfb00
%define DSC_GDTPTR 0x30
%define DSC_GDTSIZ 0x38

15
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@ -1371,7 +1371,6 @@ InitializeMpServiceData (
{
UINT32 Cr3;
UINTN Index;
PROCESSOR_SMM_DESCRIPTOR *Psd;
UINT8 *GdtTssTables;
UINTN GdtTableStepSize;
@ -1406,24 +1405,16 @@ InitializeMpServiceData (
GdtTssTables = InitGdt (Cr3, &GdtTableStepSize);
//
// Initialize PROCESSOR_SMM_DESCRIPTOR for each CPU
// Install SMI handler for each CPU
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(mCpuHotPlugData.SmBase[Index] + SMM_PSD_OFFSET);
CopyMem (Psd, &gcPsd, sizeof (gcPsd));
Psd->SmmGdtPtr = (UINT64)(UINTN)(GdtTssTables + GdtTableStepSize * Index);
Psd->SmmGdtSize = gcSmiGdtr.Limit + 1;
//
// Install SMI handler
//
InstallSmiHandler (
Index,
(UINT32)mCpuHotPlugData.SmBase[Index],
(VOID*)((UINTN)Stacks + (StackSize * Index)),
StackSize,
(UINTN)Psd->SmmGdtPtr,
Psd->SmmGdtSize,
(UINTN)(GdtTssTables + GdtTableStepSize * Index),
gcSmiGdtr.Limit + 1,
gcSmiIdtr.Base,
gcSmiIdtr.Limit + 1,
Cr3

15
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@ -711,22 +711,23 @@ PiCpuSmmEntry (
//
// Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
// specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
// is rounded up to nearest power of 2.
// specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
// This size is rounded up to nearest power of 2.
//
TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);
TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
//
// If the TileSize is larger than space available for the SMI Handler of CPU[i],
// the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
// the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
// reduced.
// If the TileSize is larger than space available for the SMI Handler of
// CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
// State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
// the SMI Handler size must be reduced or the size of the extra CPU specific
// context must be reduced.
//
ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));

26
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@ -359,31 +359,6 @@ typedef struct {
#define SMM_PSD_OFFSET 0xfb00
typedef struct {
UINT64 Signature; // Offset 0x00
UINT16 Reserved1; // Offset 0x08
UINT16 Reserved2; // Offset 0x0A
UINT16 Reserved3; // Offset 0x0C
UINT16 SmmCs; // Offset 0x0E
UINT16 SmmDs; // Offset 0x10
UINT16 SmmSs; // Offset 0x12
UINT16 SmmOtherSegment; // Offset 0x14
UINT16 Reserved4; // Offset 0x16
UINT64 Reserved5; // Offset 0x18
UINT64 Reserved6; // Offset 0x20
UINT64 Reserved7; // Offset 0x28
UINT64 SmmGdtPtr; // Offset 0x30
UINT32 SmmGdtSize; // Offset 0x38
UINT32 Reserved8; // Offset 0x3C
UINT64 Reserved9; // Offset 0x40
UINT64 Reserved10; // Offset 0x48
UINT16 Reserved11; // Offset 0x50
UINT16 Reserved12; // Offset 0x52
UINT32 Reserved13; // Offset 0x54
UINT64 Reserved14; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR;
///
/// All global semaphores' pointer
///
@ -427,7 +402,6 @@ extern EFI_PHYSICAL_ADDRESS mGdtBuffer;
extern UINTN mGdtBufferSize;
extern IA32_DESCRIPTOR gcSmiIdtr;
extern VOID *gcSmiIdtrPtr;
extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
extern UINT64 gPhyMask;
extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;
extern UINTN mSmmStackArrayBase;

2
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
View File

@ -684,7 +684,7 @@ PatchSmmSaveStateMap (
TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);
TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);

40
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
View File

@ -1,7 +1,7 @@
/** @file
Provides services to access SMRAM Save State Map
Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -23,6 +23,34 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Register/Cpuid.h>
#include <Register/SmramSaveStateMap.h>
#include "PiSmmCpuDxeSmm.h"
typedef struct {
UINT64 Signature; // Offset 0x00
UINT16 Reserved1; // Offset 0x08
UINT16 Reserved2; // Offset 0x0A
UINT16 Reserved3; // Offset 0x0C
UINT16 SmmCs; // Offset 0x0E
UINT16 SmmDs; // Offset 0x10
UINT16 SmmSs; // Offset 0x12
UINT16 SmmOtherSegment; // Offset 0x14
UINT16 Reserved4; // Offset 0x16
UINT64 Reserved5; // Offset 0x18
UINT64 Reserved6; // Offset 0x20
UINT64 Reserved7; // Offset 0x28
UINT64 SmmGdtPtr; // Offset 0x30
UINT32 SmmGdtSize; // Offset 0x38
UINT32 Reserved8; // Offset 0x3C
UINT64 Reserved9; // Offset 0x40
UINT64 Reserved10; // Offset 0x48
UINT16 Reserved11; // Offset 0x50
UINT16 Reserved12; // Offset 0x52
UINT32 Reserved13; // Offset 0x54
UINT64 Reserved14; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR;
extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
//
// EFER register LMA bit
//
@ -657,6 +685,8 @@ InstallSmiHandler (
IN UINT32 Cr3
)
{
PROCESSOR_SMM_DESCRIPTOR *Psd;
if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {
//
// Install SMI handler provided by library
@ -675,6 +705,14 @@ InstallSmiHandler (
return;
}
//
// Initialize PROCESSOR_SMM_DESCRIPTOR
//
Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + SMM_PSD_OFFSET);
CopyMem (Psd, &gcPsd, sizeof (gcPsd));
Psd->SmmGdtPtr = (UINT64)GdtBase;
Psd->SmmGdtSize = (UINT32)GdtSize;
//
// Initialize values in template before copy
//