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MdePkg/BaseLib: RISC-V: Add function to update stimecmp register

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stimecmp is a CSR supported only when Sstc extension is supported by the
platform. This register can be used to set the timer interrupt directly in
S-mode instead of going via SBI call. Add a function to update this
register.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
This commit is contained in:
Sunil V L 2023-06-24 03:38:10 +05:30 committed by mergify[bot]
parent fd629ef6e3
commit 8ae17a71af
3 changed files with 15 additions and 0 deletions
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5
MdePkg/Include/Library/BaseLib.h
View File

@ -191,6 +191,11 @@ RiscVReadTimer (
VOID VOID
); );
VOID
RiscVSetSupervisorTimeCompareRegister (
IN UINT64
);
VOID VOID
RiscVEnableTimerInterrupt ( RiscVEnableTimerInterrupt (
VOID VOID

3
MdePkg/Include/Register/RiscV64/RiscVEncoding.h
View File

@ -96,6 +96,9 @@
/* Supervisor Protection and Translation */ /* Supervisor Protection and Translation */
#define CSR_SATP 0x180 #define CSR_SATP 0x180
/* Sstc extension */
#define CSR_STIMECMP 0x14D
/* Trap/Exception Causes */ /* Trap/Exception Causes */
#define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FETCH_ACCESS 0x1 #define CAUSE_FETCH_ACCESS 0x1

7
MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
View File

@ -21,3 +21,10 @@
ASM_FUNC (RiscVReadTimer) ASM_FUNC (RiscVReadTimer)
csrr a0, CSR_TIME csrr a0, CSR_TIME
ret ret
//
// Set Supervisor Time Compare Register
//
ASM_FUNC (RiscVSetSupervisorTimeCompareRegister)
csrw CSR_STIMECMP, a0
ret