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Ring3: Refactored I/O Map initialization using PcdUartBase and PcdDebugIoPort.

This commit is contained in:
Mikhail Krichanov 2024-09-05 17:39:35 +03:00
parent ede4877e3b
commit 94be39d0c5
11 changed files with 34 additions and 12 deletions
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5
OvmfPkg/OvmfPkg.dec
View File

@ -201,9 +201,12 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeNonCcFvBase|0x0|UINT32|0x6a
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeNonCcFvSize|0x0|UINT32|0x6b
## This flag is used to control the destination port for PlatformDebugLibIoPort
## Controls the destination port for PlatformDebugLibIoPort
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4
## Controls the destination ports for SerialPortLib
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase|0x3F8|UINT16|0x104
## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and
# LUNs are retrieved from the host during virtio-scsi setup.
# MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun

4
PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
View File

@ -17,11 +17,15 @@
[Packages]
MdePkg/MdePkg.dec
OvmfPkg/OvmfPkg.dec
[LibraryClasses]
BaseLib
IoLib
PcdLib
[Sources]
SerialPortLib.c
[Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES

2
PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
View File

@ -43,7 +43,7 @@
// ---------------------------------------------
// UART Settings
// ---------------------------------------------
UINT16 gUartBase = 0x3F8;
UINT16 gUartBase = FixedPcdGet16 (PcdUartBase);
UINTN gBps = 115200;
UINT8 gData = 8;
UINT8 gStop = 1;

3
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
View File

@ -50,6 +50,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
[FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES
@ -57,6 +59,7 @@
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
OvmfPkg/OvmfPkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses.common]

7
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
View File

@ -229,12 +229,15 @@ ArchSetupExceptionStack (
Tss->SS0 = AsmReadSs ();
Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
//
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;
// and DebugIoPort = 0x402.
//
IOBitMap = (UINT8 *)((UINTN)Tss + Tss->IOMapBaseAddress);
for (Index = 0; Index < IO_BIT_MAP_SIZE; ++Index) {
if ((Index * 8) == 0x3F8) {
if ((Index * 8) == FixedPcdGet16 (PcdUartBase)) {
*IOBitMap = 0x84;
} else if ((Index * 8) == (FixedPcdGet16 (PcdDebugIoPort) - 2)) {
*IOBitMap = 0xFB;
} else {
*IOBitMap = 0xFF;
}

2
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
View File

@ -39,7 +39,7 @@ typedef struct {
(sizeof (IA32_TSS_DESCRIPTOR) * \
(FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
#define IO_BIT_MAP_SIZE (ALIGN_VALUE (0x81, 16))
#define IO_BIT_MAP_SIZE (ALIGN_VALUE (FixedPcdGet16 (PcdDebugIoPort) / 8 + 1, 16))
#define CPU_TSS_SIZE \
(sizeof (IA32_TASK_STATE_SEGMENT) * \
(FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + 1) + IO_BIT_MAP_SIZE)

5
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
View File

@ -41,6 +41,7 @@
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
OvmfPkg/OvmfPkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
@ -55,9 +56,11 @@
SynchronizationLib
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
[FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

3
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
View File

@ -50,6 +50,7 @@
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
OvmfPkg/OvmfPkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses.common]
@ -69,6 +70,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
[FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

3
UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
View File

@ -41,6 +41,7 @@
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
OvmfPkg/OvmfPkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
@ -56,6 +57,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
[FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

7
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@ -236,12 +236,15 @@ ArchSetupExceptionStack (
Tss->RSP0 = StackTop;
Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
//
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;
// and DebugIoPort = 0x402.
//
IOBitMap = (UINT8 *)((UINTN)Tss + Tss->IOMapBaseAddress);
for (Index = 0; Index < IO_BIT_MAP_SIZE; ++Index) {
if ((Index * 8) == 0x3F8) {
if ((Index * 8) == FixedPcdGet16 (PcdUartBase)) {
*IOBitMap = 0x84;
} else if ((Index * 8) == (FixedPcdGet16 (PcdDebugIoPort) - 2)) {
*IOBitMap = 0xFB;
} else {
*IOBitMap = 0xFF;
}

5
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
View File

@ -38,10 +38,7 @@ typedef struct {
} RESERVED_VECTORS_DATA;
#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
//
// 0x81 is needed to allow Ring3 code access to Uart in I/O Permission Bit Map.
//
#define IO_BIT_MAP_SIZE (ALIGN_VALUE (0x81, 16))
#define IO_BIT_MAP_SIZE (ALIGN_VALUE (FixedPcdGet16 (PcdDebugIoPort) / 8 + 1, 16))
#define CPU_TSS_SIZE (sizeof (IA32_TASK_STATE_SEGMENT) + IO_BIT_MAP_SIZE)
#endif