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ArmPkg/AArch64Mmu: remove cache maintenance for page tables 

All our page tables are allocated from memory whose cacheability
attributes are inherited by the cacheability bits in the MMU control
register, so there is no need for explicit cache maintenance after
updating the page tables. And even if there were, Set/Way operations
are not appropriate anyway for ensuring that these changes make it to
main memory. So just remove the explicit cache maintenance completely.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18570 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel 2015-10-06 12:51:07 +00:00 committed by abiesheuvel
parent 63e1c23b22
commit 9d636f57f4
1 changed files with 0 additions and 6 deletions
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6
ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
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@ -493,12 +493,6 @@ SetMemoryAttributes (
return Status; return Status;
} }
// Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
// flush and invalidate pages
ArmCleanInvalidateDataCache ();
ArmInvalidateInstructionCache ();
// Invalidate all TLB entries so changes are synced // Invalidate all TLB entries so changes are synced
ArmInvalidateTlb (); ArmInvalidateTlb ();