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ArmPkg/TimerDxe: Add ISB for timer compare value reload 

If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Heyi Guo 2018-03-15 15:17:43 +08:00 committed by Ard Biesheuvel
parent b3fa393f47
commit ac9b530e6b
1 changed files with 1 additions and 0 deletions
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ArmPkg/Drivers/TimerDxe/TimerDxe.c
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@ -338,6 +338,7 @@ TimerInterruptHandler (
// Set next compare value // Set next compare value
ArmGenericTimerSetCompareVal (CompareValue); ArmGenericTimerSetCompareVal (CompareValue);
ArmGenericTimerEnableTimer (); ArmGenericTimerEnableTimer ();
ArmInstructionSynchronizationBarrier ();
} }
gBS->RestoreTPL (OriginalTPL); gBS->RestoreTPL (OriginalTPL);