mirror of https://github.com/acidanthera/audk.git
Add SSDT for Microsoft RhProxy Driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Tim He <tim.he@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16677 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
parent
217abb4659
commit
b2499fe67e
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@ -5,7 +5,7 @@
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# All .asi files tagged with "ToolCode="DUMMY"" in following file list are device description and are included
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# by top level ASL file which will be dealed with by asl.exe application.
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#
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# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved
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#
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# This program and the accompanying materials are licensed and made available under
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# the terms and conditions of the BSD License that accompanies this distribution.
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@ -30,6 +30,7 @@
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[sources.common]
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DSDT.ASL
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RhProxy.asl
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Facs/Facs.aslc
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Facp/Facp.aslc
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Madt/Madt30.aslc
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@ -5,7 +5,7 @@
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved *;
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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@ -56,7 +56,7 @@ DefinitionBlock (
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include ("PCI_DRC.ASL")
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include ("Video.asl")
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include ("Gpe.asl")
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include ("IoTVirtualDevice.asl")
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//include ("IoTVirtualDevice.asl")
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// Sleep states supported by Chipset/Board.
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// SSx - BIOS setup controlled enabled _Sx Sleep state status
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@ -0,0 +1,166 @@
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/** @file
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SSDT for RhProxy Driver.
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)
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{
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Scope (\_SB)
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{
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//
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// Test peripheral device node for MinnowBoardMax
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//
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Device(RHPX)
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{
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Name(_HID, "MSFT8000")
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Name(_CID, "MSFT8000")
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Name(_UID, 1)
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Name(_CRS, ResourceTemplate()
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{
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// Index 0
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SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI
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1, // Device selection
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PolarityLow, // Device selection polarity
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FourWireMode, // wiremode
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8, // databit len
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ControllerInitiated, // slave mode
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8000000, // Connection speed
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ClockPolarityLow, // Clock polarity
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ClockPhaseSecond, // clock phase
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"\\_SB.SPI1", // ResourceSource: SPI bus controller name
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0, // ResourceSourceIndex
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ResourceConsumer, // Resource usage
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JSPI, // DescriptorName: creates name for offset of resource descriptor
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) // Vendor Data
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// Index 1
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I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)
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0xFF, // SlaveAddress: bus address (TBD)
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, // SlaveMode: default to ControllerInitiated
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400000, // ConnectionSpeed: in Hz
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, // Addressing Mode: default to 7 bit
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"\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))
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,
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,
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JI2C, // Descriptor Name: creates name for offset of resource descriptor
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) // VendorData
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// Index 2
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UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2
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115200, // InitialBaudRate: in bits ber second
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, // BitsPerByte: default to 8 bits
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, // StopBits: Defaults to one bit
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0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
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, // IsBigEndian: default to LittleEndian
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, // Parity: Defaults to no parity
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, // FlowControl: Defaults to no flow control
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32, // ReceiveBufferSize
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32, // TransmitBufferSize
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"\\_SB.URT2", // ResourceSource: UART bus controller name
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,
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,
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UAR2, // DescriptorName: creates name for offset of resource descriptor
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)
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// Index 3
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])
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// Index 4
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0}
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// Index 5
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])
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// Index 6
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}
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// Index 7
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])
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// Index 8
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2}
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// Index 9
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UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1
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115200, // InitialBaudRate: in bits ber second
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, // BitsPerByte: default to 8 bits
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, // StopBits: Defaults to one bit
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0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
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, // IsBigEndian: default to LittleEndian
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, // Parity: Defaults to no parity
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FlowControlHardware, // FlowControl: Defaults to no flow control
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32, // ReceiveBufferSize
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32, // TransmitBufferSize
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"\\_SB.URT1", // ResourceSource: UART bus controller name
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,
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,
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UAR1, // DescriptorName: creates name for offset of resource descriptor
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)
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// Index 10
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])
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// Index 11
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62}
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// Index 12
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])
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// Index 13
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63}
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// Index 14
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])
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// Index 15
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65}
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// Index 16
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])
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// Index 17
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64}
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// Index 18
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])
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// Index 19
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94}
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// Index 20
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])
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// Index 21
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95}
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// Index 22
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])
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// Index 23
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}
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})
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Name(_DSD, Package()
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{
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package()
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{
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// SPI Mapping
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Package(2) { "bus-SPI-SPI0", Package() { 0 }},
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// TODO: Intel will need to provide the right value for SPI0 properties
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Package(2) { "SPI0-MinClockInHz", 100 },
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Package(2) { "SPI0-MaxClockInHz", 8000000 },
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// SupportedDataBitLengths takes a list of support data bit length
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// Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},
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Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8 }},
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// I2C Mapping
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Package(2) { "bus-I2C-I2C5", Package() { 1 }},
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// UART Mapping
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Package(2) { "bus-UART-UART2", Package() { 2 }},
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Package(2) { "bus-UART-UART1", Package() { 9 }},
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}
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})
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}
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}
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}
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