mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: Use GenSmmPageTable() to create Smm S3 page table
Use GenSmmPageTable() to create both IA32 and X64 Smm S3 page table. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Dun Tan
Ray Ni
parent
701b5797b2
commit
b4dde1ae6a
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@ -18,7 +18,7 @@ InitSmmS3Cr3 (
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VOID
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VOID
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)
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)
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{
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{
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mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE);
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mSmmS3ResumeState->SmmS3Cr3 = GenSmmPageTable (PagingPae, mPhysicalAddressBits);
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return;
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return;
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}
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}
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@ -1014,136 +1014,6 @@ APHandler (
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ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
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ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
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}
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}
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/**
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Create 4G PageTable in SMRAM.
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@param[in] Is32BitPageTable Whether the page table is 32-bit PAE
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@return PageTable Address
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**/
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UINT32
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Gen4GPageTable (
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IN BOOLEAN Is32BitPageTable
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)
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{
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VOID *PageTable;
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UINTN Index;
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UINT64 *Pte;
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UINTN PagesNeeded;
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UINTN Low2MBoundary;
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UINTN High2MBoundary;
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UINTN Pages;
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UINTN GuardPage;
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UINT64 *Pdpte;
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UINTN PageIndex;
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UINTN PageAddress;
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Low2MBoundary = 0;
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High2MBoundary = 0;
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PagesNeeded = 0;
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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//
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// Add one more page for known good stack, then find the lower 2MB aligned address.
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//
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Low2MBoundary = (mSmmStackArrayBase + EFI_PAGE_SIZE) & ~(SIZE_2MB-1);
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//
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// Add two more pages for known good stack and stack guard page,
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// then find the lower 2MB aligned address.
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//
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High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1);
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PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;
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}
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//
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// Allocate the page table
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//
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PageTable = AllocatePageTableMemory (5 + PagesNeeded);
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ASSERT (PageTable != NULL);
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PageTable = (VOID *)((UINTN)PageTable);
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Pte = (UINT64 *)PageTable;
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//
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// Zero out all page table entries first
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//
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ZeroMem (Pte, EFI_PAGES_TO_SIZE (1));
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//
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// Set Page Directory Pointers
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//
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for (Index = 0; Index < 4; Index++) {
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Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask |
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(Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
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}
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Pte += EFI_PAGE_SIZE / sizeof (*Pte);
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//
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// Fill in Page Directory Entries
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//
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for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {
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Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;
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}
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Pdpte = (UINT64 *)PageTable;
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);
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GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE;
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for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {
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Pte = (UINT64 *)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
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Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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//
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// Fill in Page Table Entries
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//
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Pte = (UINT64 *)Pages;
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PageAddress = PageIndex;
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for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
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if (PageAddress == GuardPage) {
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//
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// Mark the guard page as non-present
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//
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Pte[Index] = PageAddress | mAddressEncMask;
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GuardPage += (mSmmStackSize + mSmmShadowStackSize);
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if (GuardPage > mSmmStackArrayEnd) {
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GuardPage = 0;
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}
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} else {
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Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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}
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PageAddress += EFI_PAGE_SIZE;
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}
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Pages += EFI_PAGE_SIZE;
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}
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}
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if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) {
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Pte = (UINT64 *)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
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if ((Pte[0] & IA32_PG_PS) == 0) {
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// 4K-page entries are already mapped. Just hide the first one anyway.
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Pte = (UINT64 *)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
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Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0
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} else {
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// Create 4K-page entries
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Pages = (UINTN)AllocatePageTableMemory (1);
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ASSERT (Pages != 0);
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Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
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Pte = (UINT64 *)Pages;
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PageAddress = 0;
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Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left
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for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
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PageAddress += EFI_PAGE_SIZE;
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Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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}
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}
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}
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return (UINT32)(UINTN)PageTable;
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}
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/**
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/**
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Checks whether the input token is the current used token.
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Checks whether the input token is the current used token.
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@ -35,26 +35,14 @@ InitSmmS3Cr3 (
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VOID
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VOID
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)
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)
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{
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{
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EFI_PHYSICAL_ADDRESS Pages;
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UINT64 *PTEntry;
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//
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// Generate PAE page table for the first 4GB memory space
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//
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Pages = Gen4GPageTable (FALSE);
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//
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// Fill Page-Table-Level4 (PML4) entry
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//
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PTEntry = (UINT64 *)AllocatePageTableMemory (1);
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ASSERT (PTEntry != NULL);
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*PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
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//
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//
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// Generate level4 page table for the first 4GB memory space
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// Return the address of PML4 (to set CR3)
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// Return the address of PML4 (to set CR3)
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//
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//
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mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry;
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//
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// The SmmS3Cr3 is only used by S3Resume PEIM to switch CPU from 32bit to 64bit
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//
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mSmmS3ResumeState->SmmS3Cr3 = (UINT32)GenSmmPageTable (Paging4Level, 32);
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return;
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return;
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}
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}
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