mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Remove RVCT support
RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Rebecca Cran
mergify[bot]
parent
35d9b7ea2d
commit
b55b6d33e4
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@ -1,62 +0,0 @@
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//
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// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <Library/ArmLib.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmPlatformPeiBootAction
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EXPORT ArmPlatformGetCorePosition
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EXPORT ArmPlatformGetPrimaryCoreMpId
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EXPORT ArmPlatformIsPrimaryCore
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IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore
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IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
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PRESERVE8
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AREA ArmPlatformNullHelper, CODE, READONLY
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ArmPlatformPeiBootAction FUNCTION
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bx lr
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ENDFUNC
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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ArmPlatformGetCorePosition FUNCTION
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and r1, r0, #ARM_CORE_MASK
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and r0, r0, #ARM_CLUSTER_MASK
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add r0, r1, r0, LSR #7
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bx lr
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ENDFUNC
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//UINTN
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//ArmPlatformGetPrimaryCoreMpId (
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// VOID
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// );
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ArmPlatformGetPrimaryCoreMpId FUNCTION
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mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)
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bx lr
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ENDFUNC
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//UINTN
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//ArmPlatformIsPrimaryCore (
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// IN UINTN MpId
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// );
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ArmPlatformIsPrimaryCore FUNCTION
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mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)
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and r0, r0, r1
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mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)
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cmp r0, r1
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moveq r0, #1
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movne r0, #0
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bx lr
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ENDFUNC
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END
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@ -29,7 +29,6 @@
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[Sources.Arm]
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Arm/ArmPlatformHelper.S | GCC
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Arm/ArmPlatformHelper.asm | RVCT
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[Sources.AArch64]
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AArch64/ArmPlatformHelper.S
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@ -1,118 +0,0 @@
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//
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// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AutoGen.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmPlatformStackSet
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EXPORT ArmPlatformStackSetPrimary
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EXPORT ArmPlatformStackSetSecondary
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IMPORT ArmPlatformIsPrimaryCore
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IMPORT ArmPlatformGetCorePosition
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IMPORT ArmPlatformGetPrimaryCoreMpId
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IMPORT _gPcd_FixedAtBuild_PcdCoreCount
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PRESERVE8
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AREA ArmPlatformStackLib, CODE, READONLY
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//VOID
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//ArmPlatformStackSet (
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// IN UINTN StackBase,
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// IN UINTN MpId,
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// IN UINTN PrimaryStackSize,
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// IN UINTN SecondaryStackSize
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// );
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ArmPlatformStackSet FUNCTION
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// Save parameters
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mov r6, r3
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mov r5, r2
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mov r4, r1
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mov r3, r0
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// Save the Link register
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mov r7, lr
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// Identify Stack
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mov r0, r1
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bl ArmPlatformIsPrimaryCore
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cmp r0, #1
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// Restore parameters
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mov r0, r3
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mov r1, r4
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mov r2, r5
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mov r3, r6
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// Restore the Link register
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mov lr, r7
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beq ArmPlatformStackSetPrimary
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bne ArmPlatformStackSetSecondary
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ENDFUNC
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//VOID
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//ArmPlatformStackSetPrimary (
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// IN UINTN StackBase,
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// IN UINTN MpId,
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// IN UINTN PrimaryStackSize,
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// IN UINTN SecondaryStackSize
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// );
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ArmPlatformStackSetPrimary FUNCTION
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mov r4, lr
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// Add stack of primary stack to StackBase
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add r0, r0, r2
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// Compute SecondaryCoresCount * SecondaryCoreStackSize
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mov32 r1, FixedPcdGet32 (PcdCoreCount)
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sub r1, #1
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mul r3, r3, r1
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// Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize))
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add sp, r0, r3
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bx r4
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ENDFUNC
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//VOID
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//ArmPlatformStackSetSecondary (
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// IN UINTN StackBase,
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// IN UINTN MpId,
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// IN UINTN PrimaryStackSize,
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// IN UINTN SecondaryStackSize
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// );
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ArmPlatformStackSetSecondary FUNCTION
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mov r4, lr
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mov sp, r0
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// Get Core Position
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mov r0, r1
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bl ArmPlatformGetCorePosition
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mov r5, r0
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// Get Primary Core Position
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bl ArmPlatformGetPrimaryCoreMpId
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bl ArmPlatformGetCorePosition
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// Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1)
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cmp r5, r0
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subhi r5, r5, #1
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add r5, r5, #1
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// Compute top of the secondary stack
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mul r3, r3, r5
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// Set stack
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add sp, sp, r3
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bx r4
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ENDFUNC
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END
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@ -21,7 +21,6 @@
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ArmPlatformPkg/ArmPlatformPkg.dec
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[Sources.ARM]
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Arm/ArmPlatformStackLib.asm | RVCT
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Arm/ArmPlatformStackLib.S | GCC
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[Sources.AARCH64]
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@ -1,83 +0,0 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AutoGen.h>
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IMPORT PeiCommonExceptionEntry
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EXPORT PeiVectorTable
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PRESERVE8
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AREA PrePeiCoreException, CODE, READONLY, CODEALIGN, ALIGN=5
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//============================================================
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//Default Exception Handlers
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//============================================================
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PeiVectorTable
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b _DefaultResetHandler
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b _DefaultUndefined
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b _DefaultSWI
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b _DefaultPrefetchAbort
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b _DefaultDataAbort
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b _DefaultReserved
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b _DefaultIrq
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b _DefaultFiq
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//
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// Default Exception handlers: There is no plan to return from any of these exceptions.
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// No context saving at all.
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//
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_DefaultResetHandler
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mov r1, lr
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #0
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blx PeiCommonExceptionEntry
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_DefaultUndefined
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sub r1, LR, #4
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #1
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blx PeiCommonExceptionEntry
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_DefaultSWI
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sub r1, LR, #4
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #2
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blx PeiCommonExceptionEntry
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_DefaultPrefetchAbort
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sub r1, LR, #4
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #3
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blx PeiCommonExceptionEntry
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_DefaultDataAbort
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sub r1, LR, #8
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #4
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blx PeiCommonExceptionEntry
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_DefaultReserved
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mov r1, lr
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #5
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blx PeiCommonExceptionEntry
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_DefaultIrq
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sub r1, LR, #4
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #6
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blx PeiCommonExceptionEntry
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_DefaultFiq
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sub r1, LR, #4
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cps #0x13 ; Switch to SVC for common stack
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mov r0, #7
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blx PeiCommonExceptionEntry
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END
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@ -1,89 +0,0 @@
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//
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// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AutoGen.h>
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INCLUDE AsmMacroIoLib.inc
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IMPORT CEntryPoint
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IMPORT ArmPlatformGetCorePosition
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IMPORT ArmPlatformIsPrimaryCore
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IMPORT ArmReadMpidr
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IMPORT ArmPlatformPeiBootAction
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EXPORT _ModuleEntryPoint
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PRESERVE8
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AREA PrePeiCoreEntryPoint, CODE, READONLY
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StartupAddr DCD CEntryPoint
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_ModuleEntryPoint
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// Do early platform specific actions
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bl ArmPlatformPeiBootAction
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// Identify CPU ID
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bl ArmReadMpidr
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// Keep a copy of the MpId register value
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mov r5, r0
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// Is it the Primary Core ?
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bl ArmPlatformIsPrimaryCore
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// Get the top of the primary stacks (and the base of the secondary stacks)
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mov32 r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize)
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// r0 is equal to 1 if I am the primary core
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cmp r0, #1
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beq _SetupPrimaryCoreStack
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_SetupSecondaryCoreStack
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// r1 contains the base of the secondary stacks
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// Get the Core Position
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mov r6, r1 // Save base of the secondary stacks
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mov r0, r5
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bl ArmPlatformGetCorePosition
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// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
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add r0, r0, #1
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// StackOffset = CorePos * StackSize
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mov32 r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)
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mul r0, r0, r2
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// SP = StackBase + StackOffset
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add sp, r6, r0
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_PrepareArguments
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// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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mov32 r2, FixedPcdGet32(PcdFvBaseAddress)
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ldr r1, [r2, #4]
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// Move sec startup address into a data register
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// Ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr r3, StartupAddr
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// Jump to PrePeiCore C code
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// r0 = mp_id
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// r1 = pei_core_address
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mov r0, r5
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blx r3
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_SetupPrimaryCoreStack
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mov sp, r1
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mov32 r8, FixedPcdGet64 (PcdCPUCoresStackBase)
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mov32 r9, FixedPcdGet32 (PcdInitValueInTempStack)
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mov r10, r9
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mov r11, r9
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mov r12, r9
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0:stm r8!, {r9-r12}
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cmp r8, r1
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blt 0b
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b _PrepareArguments
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_NeverReturn
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b _NeverReturn
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END
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@ -1,32 +0,0 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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EXPORT SecSwitchStack
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AREA Switch_Stack, CODE, READONLY
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;/**
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; This allows the caller to switch the stack and return
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;
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; @param StackDelta Signed amount by which to modify the stack pointer
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;
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; @return Nothing. Goes to the Entry Point passing in the new parameters
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;
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;**/
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;VOID
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;EFIAPI
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;SecSwitchStack (
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; VOID *StackDelta
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; );
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;
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SecSwitchStack
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MOV R1, SP
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ADD R1, R0, R1
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MOV SP, R1
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BX LR
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END
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@ -21,11 +21,8 @@
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[Sources.ARM]
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Arm/ArchPrePeiCore.c
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Arm/PrePeiCoreEntryPoint.asm | RVCT
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Arm/PrePeiCoreEntryPoint.S | GCC
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Arm/SwitchStack.asm | RVCT
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Arm/SwitchStack.S | GCC
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Arm/Exception.asm | RVCT
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Arm/Exception.S | GCC
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[Sources.AARCH64]
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@ -21,11 +21,8 @@
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[Sources.ARM]
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Arm/ArchPrePeiCore.c
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Arm/PrePeiCoreEntryPoint.asm | RVCT
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Arm/PrePeiCoreEntryPoint.S | GCC
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Arm/SwitchStack.asm | RVCT
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Arm/SwitchStack.S | GCC
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Arm/Exception.asm | RVCT
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Arm/Exception.S | GCC
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[Sources.AARCH64]
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@ -1,142 +0,0 @@
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//
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// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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#include <AutoGen.h>
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#include <Chipset/ArmV7.h>
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INCLUDE AsmMacroIoLib.inc
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IMPORT CEntryPoint
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IMPORT ArmPlatformIsPrimaryCore
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IMPORT ArmReadMpidr
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IMPORT ArmPlatformPeiBootAction
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IMPORT ArmPlatformStackSet
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IMPORT mSystemMemoryEnd
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EXPORT _ModuleEntryPoint
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PRESERVE8
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AREA PrePiCoreEntryPoint, CODE, READONLY
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StartupAddr DCD CEntryPoint
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_ModuleEntryPoint
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// Do early platform specific actions
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bl ArmPlatformPeiBootAction
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// Get ID of this CPU in multi-core system
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bl ArmReadMpidr
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// Keep a copy of the MpId register value
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mov r8, r0
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_SetSVCMode
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// Enter SVC mode, Disable FIQ and IRQ
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mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)
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msr CPSR_c, r1
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// Check if we can install the stack at the top of the System Memory or if we need
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// to install the stacks at the bottom of the Firmware Device (case the FD is located
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// at the top of the DRAM)
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_SystemMemoryEndInit
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adrll r1, mSystemMemoryEnd
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ldrd r2, r3, [r1]
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teq r3, #0
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moveq r1, r2
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mvnne r1, #0
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_SetupStackPosition
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// r1 = SystemMemoryTop
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// Calculate Top of the Firmware Device
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mov32 r2, FixedPcdGet32(PcdFdBaseAddress)
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mov32 r3, FixedPcdGet32(PcdFdSize)
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sub r3, r3, #1
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add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize
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// UEFI Memory Size (stacks are allocated in this region)
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mov32 r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize)
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//
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// Reserve the memory for the UEFI region (contain stacks on its top)
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//
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// Calculate how much space there is between the top of the Firmware and the Top of the System Memory
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subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop
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bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM
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cmp r0, r4
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bge _SetupStack
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// Case the top of stacks is the FdBaseAddress
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mov r1, r2
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_SetupStack
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// r1 contains the top of the stack (and the UEFI Memory)
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// Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
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// one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
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// top of the memory space)
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adds r9, r1, #1
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bcs _SetupOverflowStack
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_SetupAlignedStack
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mov r1, r9
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b _GetBaseUefiMemory
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_SetupOverflowStack
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// Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
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// aligned (4KB)
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mov32 r9, EFI_PAGE_MASK
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and r9, r9, r1
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sub r1, r1, r9
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_GetBaseUefiMemory
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// Calculate the Base of the UEFI Memory
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sub r9, r1, r4
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|
||||
_GetStackBase
|
||||
// r1 = The top of the Mpcore Stacks
|
||||
// Stack for the primary core = PrimaryCoreStack
|
||||
mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)
|
||||
sub r10, r1, r2
|
||||
|
||||
// Stack for the secondary core = Number of Cores - 1
|
||||
mov32 r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize)
|
||||
sub r10, r10, r1
|
||||
|
||||
// r10 = The base of the MpCore Stacks (primary stack & secondary stacks)
|
||||
mov r0, r10
|
||||
mov r1, r8
|
||||
//ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
|
||||
mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)
|
||||
mov32 r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)
|
||||
bl ArmPlatformStackSet
|
||||
|
||||
// Is it the Primary Core ?
|
||||
mov r0, r8
|
||||
bl ArmPlatformIsPrimaryCore
|
||||
cmp r0, #1
|
||||
bne _PrepareArguments
|
||||
|
||||
_PrepareArguments
|
||||
mov r0, r8
|
||||
mov r1, r9
|
||||
mov r2, r10
|
||||
|
||||
// Move sec startup address into a data register
|
||||
// Ensure we're jumping to FV version of the code (not boot remapped alias)
|
||||
ldr r4, StartupAddr
|
||||
|
||||
// Jump to PrePiCore C code
|
||||
// r0 = MpId
|
||||
// r1 = UefiMemoryBase
|
||||
// r2 = StacksBase
|
||||
blx r4
|
||||
|
||||
_NeverReturn
|
||||
b _NeverReturn
|
||||
|
||||
END
|
||||
|
|
@ -22,7 +22,6 @@
|
|||
[Sources.ARM]
|
||||
Arm/ArchPrePi.c
|
||||
Arm/ModuleEntryPoint.S | GCC
|
||||
Arm/ModuleEntryPoint.asm | RVCT
|
||||
|
||||
[Sources.AArch64]
|
||||
AArch64/ArchPrePi.c
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@
|
|||
[Sources.ARM]
|
||||
Arm/ArchPrePi.c
|
||||
Arm/ModuleEntryPoint.S | GCC
|
||||
Arm/ModuleEntryPoint.asm | RVCT
|
||||
|
||||
[Sources.AArch64]
|
||||
AArch64/ArchPrePi.c
|
||||
|
|
|
|||
|
|
@ -5,10 +5,7 @@
|
|||
#
|
||||
#*/
|
||||
|
||||
# Define the following variable to specify an alternative toolchain to the one located in your PATH:
|
||||
# - RVCT_TOOLS_PATH: for RVCT and RVCTLINUX toolchains
|
||||
|
||||
EDK2_TOOLCHAIN ?= RVCTLINUX
|
||||
EDK2_TOOLCHAIN ?= GCC5
|
||||
EDK2_ARCH ?= ARM
|
||||
EDK2_BUILD ?= DEBUG
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue