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MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code 

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
This commit is contained in:
Ruiyu Ni 2018-09-21 15:22:46 +08:00
parent bff6584d1f
commit b8bfb92b4e
1 changed files with 12 additions and 14 deletions
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26
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
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@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
#define NO_MAPPING (VOID *) (UINTN) -1 #define NO_MAPPING (VOID *) (UINTN) -1
#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
@ -122,25 +124,25 @@ CreateRootBridge (
// //
// Make sure Mem and MemAbove4G apertures are valid // Make sure Mem and MemAbove4G apertures are valid
// //
if (Bridge->Mem.Base <= Bridge->Mem.Limit) { if (RESOURCE_VALID (&Bridge->Mem)) {
ASSERT (Bridge->Mem.Limit < SIZE_4GB); ASSERT (Bridge->Mem.Limit < SIZE_4GB);
if (Bridge->Mem.Limit >= SIZE_4GB) { if (Bridge->Mem.Limit >= SIZE_4GB) {
return NULL; return NULL;
} }
} }
if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) { if (RESOURCE_VALID (&Bridge->MemAbove4G)) {
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB); ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
if (Bridge->MemAbove4G.Base < SIZE_4GB) { if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL; return NULL;
} }
} }
if (Bridge->PMem.Base <= Bridge->PMem.Limit) { if (RESOURCE_VALID (&Bridge->PMem)) {
ASSERT (Bridge->PMem.Limit < SIZE_4GB); ASSERT (Bridge->PMem.Limit < SIZE_4GB);
if (Bridge->PMem.Limit >= SIZE_4GB) { if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL; return NULL;
} }
} }
if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) { if (RESOURCE_VALID (&Bridge->PMemAbove4G)) {
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB); ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
if (Bridge->PMemAbove4G.Base < SIZE_4GB) { if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
return NULL; return NULL;
@ -157,11 +159,9 @@ CreateRootBridge (
// support separate windows for Non-prefetchable and Prefetchable // support separate windows for Non-prefetchable and Prefetchable
// memory. // memory.
// //
ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit); ASSERT (!RESOURCE_VALID (&Bridge->PMem));
ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));
if ((Bridge->PMem.Base <= Bridge->PMem.Limit) || if (RESOURCE_VALID (&Bridge->PMem) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {
(Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
) {
return NULL; return NULL;
} }
} }
@ -171,11 +171,9 @@ CreateRootBridge (
// If this bit is not set, then the PCI Root Bridge does not support // If this bit is not set, then the PCI Root Bridge does not support
// 64 bit memory windows. // 64 bit memory windows.
// //
ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit); ASSERT (!RESOURCE_VALID (&Bridge->MemAbove4G));
ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit); ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));
if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) || if (RESOURCE_VALID (&Bridge->MemAbove4G) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {
(Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
) {
return NULL; return NULL;
} }
} }