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CorebootModulePkg/BaseSerialPortLib: Set DTR and RTS 

Ensure communication between the host and the UEFI system running
CorebootPayloadPkg.  In cases where the host has flow control enabled
and the serial connection is providing the flow control signals, the
host will not be able to send data to the UEFI system because DTR and
RTS are not present.  The host may also discard all output data from
the UEFI system because DTR is not present.  By setting DTR and RTS
in the UART initialization code this case works properly.

Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
This commit is contained in:
Leahy, Leroy P 2016-05-09 10:57:08 -07:00 committed by Prince Agyeman
parent b08993bd13
commit bb0831670f
1 changed files with 3 additions and 2 deletions
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5
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
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@ -554,9 +554,10 @@ SerialPortInitialize (
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
// //
// Put Modem Control Register(MCR) into its reset state of 0x00. // Set RTS and DTR in Modem Control Register(MCR)
// //
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }