mirror of https://github.com/acidanthera/audk.git
CpuPageTableLib: Avoid treating non-leaf entry as leaf one
Today's logic wrongly treats the non-leaf entry as leaf entry and updates its paging attributes. The patch fixes the bug to only update paging attributes for non-present entries or leaf entries. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
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@ -248,6 +248,7 @@ PageTableLibMapInLevel (
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UINTN BitStart;
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UINTN Index;
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IA32_PAGING_ENTRY *PagingEntry;
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IA32_PAGING_ENTRY *CurrentPagingEntry;
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UINT64 RegionLength;
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UINT64 SubLength;
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UINT64 SubOffset;
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@ -359,18 +360,20 @@ PageTableLibMapInLevel (
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//
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PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
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while (Offset < Length && Index < 512) {
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SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
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CurrentPagingEntry = (!Modify && CreateNew) ? &OneOfPagingEntry : &PagingEntry[Index];
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SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
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if ((Level <= MaxLeafLevel) &&
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(((LinearAddress + Offset) & RegionMask) == 0) &&
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(((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
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(SubLength == RegionLength)
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(SubLength == RegionLength) &&
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((CurrentPagingEntry->Pce.Present == 0) || IsPle (CurrentPagingEntry, Level))
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)
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{
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//
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// Create one entry mapping the entire region (1G, 2M or 4K).
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//
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if (Modify) {
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PageTableLibSetPle (Level, &PagingEntry[Index], Offset, Attribute, Mask);
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PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, Mask);
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}
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} else {
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//
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@ -382,7 +385,7 @@ PageTableLibMapInLevel (
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// but the length is SMALLER than the RegionLength.
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//
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Status = PageTableLibMapInLevel (
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(!Modify && CreateNew) ? &OneOfPagingEntry : &PagingEntry[Index],
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CurrentPagingEntry,
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Modify,
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Buffer,
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BufferSize,
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