mirror of https://github.com/acidanthera/audk.git
CpuPageTableLib: Avoid treating non-leaf entry as leaf one
Today's logic wrongly treats the non-leaf entry as leaf entry and updates its paging attributes. The patch fixes the bug to only update paging attributes for non-present entries or leaf entries. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
parent
9cb8974f06
commit
c16f02f776
|
@ -248,6 +248,7 @@ PageTableLibMapInLevel (
|
||||||
UINTN BitStart;
|
UINTN BitStart;
|
||||||
UINTN Index;
|
UINTN Index;
|
||||||
IA32_PAGING_ENTRY *PagingEntry;
|
IA32_PAGING_ENTRY *PagingEntry;
|
||||||
|
IA32_PAGING_ENTRY *CurrentPagingEntry;
|
||||||
UINT64 RegionLength;
|
UINT64 RegionLength;
|
||||||
UINT64 SubLength;
|
UINT64 SubLength;
|
||||||
UINT64 SubOffset;
|
UINT64 SubOffset;
|
||||||
|
@ -359,18 +360,20 @@ PageTableLibMapInLevel (
|
||||||
//
|
//
|
||||||
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
|
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
|
||||||
while (Offset < Length && Index < 512) {
|
while (Offset < Length && Index < 512) {
|
||||||
SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
|
CurrentPagingEntry = (!Modify && CreateNew) ? &OneOfPagingEntry : &PagingEntry[Index];
|
||||||
|
SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
|
||||||
if ((Level <= MaxLeafLevel) &&
|
if ((Level <= MaxLeafLevel) &&
|
||||||
(((LinearAddress + Offset) & RegionMask) == 0) &&
|
(((LinearAddress + Offset) & RegionMask) == 0) &&
|
||||||
(((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
|
(((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
|
||||||
(SubLength == RegionLength)
|
(SubLength == RegionLength) &&
|
||||||
|
((CurrentPagingEntry->Pce.Present == 0) || IsPle (CurrentPagingEntry, Level))
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
//
|
//
|
||||||
// Create one entry mapping the entire region (1G, 2M or 4K).
|
// Create one entry mapping the entire region (1G, 2M or 4K).
|
||||||
//
|
//
|
||||||
if (Modify) {
|
if (Modify) {
|
||||||
PageTableLibSetPle (Level, &PagingEntry[Index], Offset, Attribute, Mask);
|
PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, Mask);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
//
|
//
|
||||||
|
@ -382,7 +385,7 @@ PageTableLibMapInLevel (
|
||||||
// but the length is SMALLER than the RegionLength.
|
// but the length is SMALLER than the RegionLength.
|
||||||
//
|
//
|
||||||
Status = PageTableLibMapInLevel (
|
Status = PageTableLibMapInLevel (
|
||||||
(!Modify && CreateNew) ? &OneOfPagingEntry : &PagingEntry[Index],
|
CurrentPagingEntry,
|
||||||
Modify,
|
Modify,
|
||||||
Buffer,
|
Buffer,
|
||||||
BufferSize,
|
BufferSize,
|
||||||
|
|
Loading…
Reference in New Issue