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ARM Packages: Fixed mispellings

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Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13502 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-07-04 20:23:21 +00:00
parent 3bb46df2a3
commit ce88684e2a
6 changed files with 8 additions and 8 deletions
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2
ArmPkg/Drivers/CpuDxe/Mmu.c
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@ -784,7 +784,7 @@ ConvertSectionToPages (
// formulate page table entry, Domain=0, NS=0 // formulate page table entry, Domain=0, NS=0
PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
// write the page table entry out, repalcing section entry // write the page table entry out, replacing section entry
FirstLevelTable[FirstLevelIdx] = PageTableDescriptor; FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
return EFI_SUCCESS; return EFI_SUCCESS;

2
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -99,7 +99,7 @@ ArmGicEnableInterruptInterface (
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
// Enable CPU interface in Secure world // Enable CPU interface in Secure world
// Enable CPU inteface in Non-secure World // Enable CPU interface in Non-secure World
// Signal Secure Interrupts to CPU using FIQ line * // Signal Secure Interrupts to CPU using FIQ line *
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_SECURE |

6
ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
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@ -54,7 +54,7 @@ TimerConstructor (
ASSERT (TimerFreq); ASSERT (TimerFreq);
} else { } else {
DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, Hence cann't use this library \n")); DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library can not be used.\n"));
ASSERT (0); ASSERT (0);
} }
@ -79,7 +79,7 @@ MicroSecondDelay (
UINT64 TimerTicks64; UINT64 TimerTicks64;
UINT64 SystemCounterVal; UINT64 SystemCounterVal;
// Calculate counter ticks that can represent requsted delay // Calculate counter ticks that can represent requested delay
TimerTicks64 = MultU64x32 (MicroSeconds, TICKS_PER_MICRO_SEC); TimerTicks64 = MultU64x32 (MicroSeconds, TICKS_PER_MICRO_SEC);
// Read System Counter value // Read System Counter value
@ -106,7 +106,7 @@ MicroSecondDelay (
@param NanoSeconds The minimum number of nanoseconds to delay. @param NanoSeconds The minimum number of nanoseconds to delay.
@return The value of NanoSeconds inputted. @return The value of NanoSeconds inputed.
**/ **/
UINTN UINTN

2
ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
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@ -83,7 +83,7 @@ ArmArchTimerReadReg (
case CnthpTval: case CnthpTval:
case CnthpCtl: case CnthpCtl:
case CnthpCval: case CnthpCval:
DEBUG ((EFI_D_ERROR, "The register is related to Hyperviser Mode. Can't perform requested operation\n ")); DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
break; break;
default: default:

2
ArmPlatformPkg/PrePi/ModuleEntryPoint.S
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@ -108,7 +108,7 @@ _GetStackBaseMpCore:
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)
sub r7, r1, r2 sub r7, r1, r2
// Stack for the secondary core = Number of Cluster * (4 Core per cluster) * SecondaryStackSize // Stack for the secondary core = Number of Clusters * (4 Cores per cluster) * SecondaryStackSize
LoadConstantToReg (FixedPcdGet32(PcdClusterCount), r2) LoadConstantToReg (FixedPcdGet32(PcdClusterCount), r2)
lsl r2, r2, #2 lsl r2, r2, #2
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3) LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)

2
ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
View File

@ -109,7 +109,7 @@ _GetStackBaseMpCore
LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2) LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)
sub r7, r1, r2 sub r7, r1, r2
// Stack for the secondary core = Number of Cluster * (4 Core per cluster) * SecondaryStackSize // Stack for the secondary core = Number of Clusters * (4 Cores per cluster) * SecondaryStackSize
LoadConstantToReg (FixedPcdGet32(PcdClusterCount), r2) LoadConstantToReg (FixedPcdGet32(PcdClusterCount), r2)
lsl r2, r2, #2 lsl r2, r2, #2
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3) LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)