mirror of https://github.com/acidanthera/audk.git
Ring3: Set USER bit in all page table structures.
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@ -377,7 +377,7 @@ Split2MPageTo4K (
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//
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// Fill in 2M page entry.
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//
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*PageEntry2M = (UINT64)(UINTN)PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
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*PageEntry2M = (UINT64)(UINTN)PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW | IA32_PG_U;
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PhysicalAddress4K = PhysicalAddress;
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for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {
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@ -459,7 +459,7 @@ Split1GPageTo2M (
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//
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// Fill in 1G page entry.
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//
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*PageEntry1G = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
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*PageEntry1G = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW | IA32_PG_U;
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PhysicalAddress2M = PhysicalAddress;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {
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@ -591,6 +591,8 @@ SetPageTablePoolReadOnly (
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IA32_PG_P | IA32_PG_RW;
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if (Level > 2) {
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NewPageTable[EntryIndex] |= IA32_PG_PS;
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} else {
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NewPageTable[EntryIndex] |= IA32_PG_U;
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}
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PhysicalAddress += LevelSize[Level - 1];
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@ -861,9 +863,10 @@ CreateIdentityMappingPageTables (
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//
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// Make a PML5 Entry
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//
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PageMapLevel5Entry->Uint64 = (UINT64)(UINTN)PageMapLevel4Entry | AddressEncMask;
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PageMapLevel5Entry->Bits.ReadWrite = 1;
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PageMapLevel5Entry->Bits.Present = 1;
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PageMapLevel5Entry->Uint64 = (UINT64)(UINTN)PageMapLevel4Entry | AddressEncMask;
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PageMapLevel5Entry->Bits.ReadWrite = 1;
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PageMapLevel5Entry->Bits.UserSupervisor = 1;
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PageMapLevel5Entry->Bits.Present = 1;
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PageMapLevel5Entry++;
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}
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@ -881,9 +884,10 @@ CreateIdentityMappingPageTables (
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//
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// Make a PML4 Entry
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//
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PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;
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PageMapLevel4Entry->Bits.ReadWrite = 1;
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PageMapLevel4Entry->Bits.Present = 1;
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PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;
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PageMapLevel4Entry->Bits.ReadWrite = 1;
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PageMapLevel4Entry->Bits.UserSupervisor = 1;
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PageMapLevel4Entry->Bits.Present = 1;
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if (Page1GSupport) {
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PageDirectory1GEntry = (VOID *)PageDirectoryPointerEntry;
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@ -916,9 +920,10 @@ CreateIdentityMappingPageTables (
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.UserSupervisor = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
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if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize, GhcbBase, GhcbSize)) {
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@ -145,6 +145,7 @@ typedef union {
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_U BIT2
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#define IA32_PG_PS BIT7
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#define PAGING_PAE_INDEX_MASK 0x1FF
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@ -38,7 +38,7 @@
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#define IA32_PG_NX BIT63
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#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)
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#define PAGE_ATTRIBUTE_BITS_POST_SPLIT (IA32_PG_RW | IA32_PG_P)
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#define PAGE_ATTRIBUTE_BITS_POST_SPLIT (IA32_PG_RW | IA32_PG_P | IA32_PG_U)
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//
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// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
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@ -398,6 +398,10 @@ GetAttributesFromPageEntry (
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Attributes |= EFI_MEMORY_XP;
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}
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if ((*PageEntry & IA32_PG_U) != 0) {
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Attributes |= EFI_MEMORY_USER;
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}
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return Attributes;
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}
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@ -1013,9 +1017,9 @@ RefreshGcdMemoryAttributesFromPaging (
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PageLength = 0;
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if (IsExecuteDisableEnabled ()) {
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Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;
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Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_USER;
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} else {
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Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP;
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Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_USER;
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}
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for (Index = 0; Index < NumberOfDescriptors; Index++) {
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