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UefiCpuPkg/ResetVector: Modify Page Table in ResetVector 

In ResetVector, if create page table, its highest address is fixed
because after page table, code layout is fixed(4K for normal code,
and another 4K only contains reset vector code).
Today's implementation organizes the page table as following if 1G
page table is used:
  4G-16K: PML4 page (PML4[0] points to 4G-12K)
  4G-12K: PDP page
  CR3 is set to 4G-16K
When 2M page table is used, the layout is as following:
  4G-32K: PML4 page (PML4[0] points to 4G-28K)
  4G-28K: PDP page (PDP entries point to PD pages)
  4G-24K: PD page mapping 0-1G
  4G-20K: PD page mapping 1-2G
  4G-16K: PD page mapping 2-3G
  4G-12K: PD page mapping 3-4G
  CR3 is set to 4G-32K
CR3 doesn't point to a fixed location which is a bit hard to debug at
runtime.

The new page table layout will always put PML4 in highest address
When 1G page table is used, the layout is as following:
  4G-16K: PDP page
  4G-12K: PML4 page (PML4[0] points to 4G-16K)
When 2M page table is used, the layout is as following:
  4G-32K: PD page mapping 0-1G
  4G-28K: PD page mapping 1-2G
  4G-24K: PD page mapping 2-3G
  4G-20K: PD page mapping 3-4G
  4G-16K: PDP page (PDP entries point to PD pages)
  4G-12K: PML4 page (PML4[0] points to 4G-16K)
CR3 is always set to 4G-12K
So, this patch can improve debuggability by make sure the init
CR3 pointing to a fixed address(4G-12K).

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Liu, Zhiguang 2023-05-08 16:15:03 +08:00 committed by mergify[bot]
parent 0fba57da65
commit d064a6f790
1 changed files with 17 additions and 16 deletions
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33
UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
View File

@ -41,13 +41,6 @@ BITS 64
ALIGN 16
Pml4:
;
; PML4 (1 * 512GB entry)
;
DQ PAGE_NLE(Pdp)
TIMES 0x1000 - ($ - Pml4) DB 0
%ifdef PAGE_TABLE_1G
Pdp:
;
@ -59,15 +52,6 @@ Pdp:
%assign i i+1
%endrep
%else
Pdp:
;
; Page-directory pointer table (4 * 1GB entries => 4GB)
;
DQ PAGE_NLE(Pd)
DQ PAGE_NLE(Pd + 0x1000)
DQ PAGE_NLE(Pd + 0x2000)
DQ PAGE_NLE(Pd + 0x3000)
TIMES 0x1000 - ($ - Pdp) DB 0
Pd:
;
@ -79,5 +63,22 @@ Pd:
DQ PAGE_PDE_2MB(i)
%assign i i+1
%endrep
Pdp:
;
; Page-directory pointer table (4 * 1GB entries => 4GB)
;
DQ PAGE_NLE(Pd)
DQ PAGE_NLE(Pd + 0x1000)
DQ PAGE_NLE(Pd + 0x2000)
DQ PAGE_NLE(Pd + 0x3000)
TIMES 0x1000 - ($ - Pdp) DB 0
%endif
Pml4:
;
; PML4 (1 * 512GB entry)
;
DQ PAGE_NLE(Pdp)
TIMES 0x1000 - ($ - Pml4) DB 0
EndOfPageTables: