UefiCpuPkg/PiSmmCpuDxeSmm: use mnemonics for FXSAVE(64)/FXRSTOR(64)

NASM introduced FXSAVE / FXRSTOR support in commit 900fa5b26b8f ("NASM
0.98p3-hpa", 2002-04-30), which commit stands for the nasm-0.98p3-hpa
release.

NASM introduced FXSAVE64 / FXRSTOR64 support in commit 3a014348ca15
("insns: add FXSAVE64/FXRSTOR64, drop np prefix", 2010-07-07), which was
part of the "nasm-2.09" release.

Edk2 requires nasm-2.10 or later for use with the GCC toolchain family,
and nasm-2.12.01 or later for use with all other toolchain families.
Replace the binary encoding of the FXSAVE(64)/FXRSTOR(64) instructions
with mnemonics.

I verified that the "Ia32/SmiException.obj", "X64/SmiEntry.obj" and
"X64/SmiException.obj" files are rebuilt after this patch, without any
change in content.

This patch removes the last instructions encoded with DBs from
PiSmmCpuDxeSmm.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm

@@ -382,7 +382,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 ;; FX_SAVE_STATE_IA32 FxSaveState;
     sub     esp, 512
     mov     edi, esp
-    db      0xf, 0xae, 0x7 ;fxsave [edi]
+    fxsave  [edi]
 
 ; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
     cld
@@ -410,7 +410,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 
 ;; FX_SAVE_STATE_IA32 FxSaveState;
     mov     esi, esp
-    db      0xf, 0xae, 0xe ; fxrstor [esi]
+    fxrstor [esi]
     add     esp, 512
 
 ;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
@@ -582,7 +582,7 @@ PFHandlerEntry:
     clts
     sub     esp, 512
     mov     edi, esp
-    db      0xf, 0xae, 0x7 ;fxsave [edi]
+    fxsave  [edi]
 
 ; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
     cld
@@ -612,7 +612,7 @@ PFHandlerEntry:
 
 ;; FX_SAVE_STATE_IA32 FxSaveState;
     mov     esi, esp
-    db      0xf, 0xae, 0xe ; fxrstor [esi]
+    fxrstor [esi]
     add     esp, 512
 
 ;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;

UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm

@@ -182,8 +182,7 @@ _SmiHandler:
     ; Save FP registers
     ;
     sub     rsp, 0x200
-    DB      0x48                         ; FXSAVE64
-    fxsave  [rsp]
+    fxsave64 [rsp]
 
     add     rsp, -0x20
 
@@ -201,8 +200,7 @@ _SmiHandler:
     ;
     ; Restore FP registers
     ;
-    DB      0x48                         ; FXRSTOR64
-    fxrstor [rsp]
+    fxrstor64 [rsp]
 
     add     rsp, 0x200
 

UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm

@@ -279,7 +279,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 
     sub rsp, 512
     mov rdi, rsp
-    db 0xf, 0xae, 00000111y ;fxsave [rdi]
+    fxsave [rdi]
 
 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
     cld
@@ -309,7 +309,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 ;; FX_SAVE_STATE_X64 FxSaveState;
 
     mov rsi, rsp
-    db 0xf, 0xae, 00001110y ; fxrstor [rsi]
+    fxrstor [rsi]
     add rsp, 512
 
 ;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;