mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformPei: honor extended TSEG in PcdQ35TsegMbytes if available
Recognize an extended TSEG when available in Q35TsegMbytesInitialization(), and set both PcdQ35TsegMbytes (for OvmfPkg/SmmAccess) and "mQ35TsegMbytes" (for PlatformPei's own use) accordingly. The new logic interfaces with the QEMU feature added in QEMU commit 2f295167e0c4 ("q35/mch: implement extended TSEG sizes", 2017-06-08). At this point we have to explicitly restrict Q35TsegMbytesInitialization() to the Q35 board, but that's OK, because Q35TsegMbytesInitialization() is only called when PcdSmmSmramRequire is set, and for that Q35 is already an enforced requirement. Cc: Jordan Justen <jordan.l.justen@intel.com> Suggested-by: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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@ -19,16 +19,19 @@ Module Name:
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//
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// The package level header files this module uses
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//
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#include <IndustryStandard/Q35MchIch9.h>
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Library/MtrrLib.h>
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@ -49,7 +52,54 @@ Q35TsegMbytesInitialization (
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VOID
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)
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{
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mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
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UINT16 ExtendedTsegMbytes;
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RETURN_STATUS PcdStatus;
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if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
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"only DID=0x%04x (Q35) is supported\n",
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__FUNCTION__,
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mHostBridgeDevId,
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INTEL_Q35_MCH_DEVICE_ID
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));
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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//
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// Check if QEMU offers an extended TSEG.
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//
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// This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
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// register, and reading back the register.
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//
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// On a QEMU machine type that does not offer an extended TSEG, the initial
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// write overwrites whatever value a malicious guest OS may have placed in
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// the (unimplemented) register, before entering S3 or rebooting.
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// Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
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//
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// On a QEMU machine type that offers an extended TSEG, the initial write
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// triggers an update to the register. Subsequently, the value read back
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// (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
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// number of megabytes.
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//
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PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
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ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
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if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
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mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
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return;
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}
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DEBUG ((
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DEBUG_INFO,
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"%a: QEMU offers an extended TSEG (%d MB)\n",
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__FUNCTION__,
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ExtendedTsegMbytes
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));
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PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
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ASSERT_RETURN_ERROR (PcdStatus);
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mQ35TsegMbytes = ExtendedTsegMbytes;
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}
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@ -645,6 +645,11 @@ InitializePlatform (
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AddressWidthInitialization ();
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MaxCpuCountInitialization ();
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//
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// Query Host Bridge DID
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//
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mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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Q35TsegMbytesInitialization ();
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}
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@ -658,11 +663,6 @@ InitializePlatform (
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InitializeXen ();
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}
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//
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// Query Host Bridge DID
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//
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mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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if (mBootMode != BOOT_ON_S3_RESUME) {
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if (!FeaturePcdGet (PcdSmmSmramRequire)) {
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ReserveEmuVariableNvStore ();
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@ -108,4 +108,6 @@ extern UINT8 mPhysMemAddressWidth;
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extern UINT32 mMaxCpuCount;
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extern UINT16 mHostBridgeDevId;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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