tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ArmPlatformPkg/ArmVExpressPkg: Introduce the PcdNorFlashRemapping feature PCD 

Platform designers can decide to not remap the DRAM at 0x0 on the VExpress motherboard.
This PCD can be used to set this feature.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11807 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-06-11 12:08:36 +00:00
parent 1ad14bc86b
commit d6b5f236ae
5 changed files with 106 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
ArmPlatformPkg/ArmPlatformPkg.dec
View File

@ -40,23 +40,25 @@
[PcdsFeatureFlag.common]
gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE|BOOLEAN|0x00000001
# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
[PcdsFixedAtBuild.common]
# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003
# Stack for CPU Cores in Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000006
# Stack for CPU Cores in Secure Monitor Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000006
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000007
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0|UINT32|0x00000008
# Stack for CPU Cores in Non Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000008
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x00000009
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0|UINT32|0x00000009
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0|UINT32|0x0000000A
# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015

1
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
View File

@ -44,6 +44,7 @@
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress

1
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
View File

@ -45,6 +45,7 @@
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
gArmPlatformTokenSpaceGuid.PcdStandalone
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress

11
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
View File

@ -178,9 +178,14 @@ ArmPlatformBootRemapping (
VOID
)
{
UINT32 val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
// we remap the DRAM to 0x0
MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (val32 & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
UINT32 Value;
if (FeaturePcdGet(PcdNorFlashRemapping)) {
SerialPrint ("Secure ROM at 0x0\n\r");
} else {
Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
// Remap the DRAM to 0x0
MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
}
/**

40
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
View File

@ -18,6 +18,9 @@
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
// Number of Virtual Memory Map Descriptors without a Logic Tile
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
@ -34,24 +37,26 @@
entry
**/
VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {
UINT32 val32;
UINT32 CacheAttributes;
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
BOOLEAN bTrustzoneSupport;
UINTN Index = 0;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
ASSERT(VirtualMemoryMap != NULL);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
// Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.
// As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case
val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG);
if (ARM_VE_CFGRW1_TZASC_EN_BIT_MASK & val32) {
if (ArmPlatformTrustzoneSupported ()) {
bTrustzoneSupport = TRUE;
} else {
bTrustzoneSupport = FALSE;
@ -67,13 +72,24 @@ VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemory
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
if (FeaturePcdGet(PcdNorFlashRemapping)) {
// Map the NOR Flash as Secure Memory
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_SECURE_CACHED;
} else {
VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_SECURE_UNCACHED;
}
} else {
// DRAM mapping
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
// DDR
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// SMC CS7
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;
@ -91,7 +107,7 @@ VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemory
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// SMB CS3-CS6 - Motherboard Peripherals
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
@ -105,6 +121,10 @@ VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemory
VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;
VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);
ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
} else {
ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
}
// End of Table
@ -117,7 +137,7 @@ VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemory
}
/**
Return the EFI Memory Map of your platform
Return the EFI Memory Map provided by extension memory on your platform
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
Descriptor HOBs used by DXE core.