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UefiCpuPkg: Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h

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Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove
extern for mSmmShadowStackSize in c files to simplify code.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Dun Tan 2023-04-10 09:06:42 +08:00 committed by Ray Ni
parent ef64ae06f8
commit d706d9c64a
5 changed files with 3 additions and 8 deletions
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3
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
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@ -1,7 +1,7 @@
/** @file /** @file
SMM CPU misc functions for Ia32 arch specific. SMM CPU misc functions for Ia32 arch specific.
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -14,7 +14,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer;
UINTN mGdtBufferSize; UINTN mGdtBufferSize;
extern BOOLEAN mCetSupported; extern BOOLEAN mCetSupported;
extern UINTN mSmmShadowStackSize;
X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;

2
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
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@ -29,8 +29,6 @@ MM_COMPLETION mSmmStartupThisApToken;
// //
UINT32 *mPackageFirstThreadIndex = NULL; UINT32 *mPackageFirstThreadIndex = NULL;
extern UINTN mSmmShadowStackSize;
/** /**
Performs an atomic compare exchange operation to get semaphore. Performs an atomic compare exchange operation to get semaphore.
The compare exchange operation must be performed using The compare exchange operation must be performed using

1
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
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@ -264,6 +264,7 @@ extern EFI_SMM_CPU_PROTOCOL mSmmCpu;
extern EFI_MM_MP_PROTOCOL mSmmMp; extern EFI_MM_MP_PROTOCOL mSmmMp;
extern BOOLEAN m5LevelPagingNeeded; extern BOOLEAN m5LevelPagingNeeded;
extern PAGING_MODE mPagingMode; extern PAGING_MODE mPagingMode;
extern UINTN mSmmShadowStackSize;
/// ///
/// The mode of the CPU at the time an SMI occurs /// The mode of the CPU at the time an SMI occurs

2
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
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@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define PAGE_TABLE_PAGES 8 #define PAGE_TABLE_PAGES 8
#define ACC_MAX_BIT BIT3 #define ACC_MAX_BIT BIT3
extern UINTN mSmmShadowStackSize;
LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);
BOOLEAN m1GPageTableSupport = FALSE; BOOLEAN m1GPageTableSupport = FALSE;
BOOLEAN mCpuSmmRestrictedMemoryAccess; BOOLEAN mCpuSmmRestrictedMemoryAccess;

3
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
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@ -1,7 +1,7 @@
/** @file /** @file
SMM CPU misc functions for x64 arch specific. SMM CPU misc functions for x64 arch specific.
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -12,7 +12,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer;
UINTN mGdtBufferSize; UINTN mGdtBufferSize;
extern BOOLEAN mCetSupported; extern BOOLEAN mCetSupported;
extern UINTN mSmmShadowStackSize;
X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;