mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type check
This is the AARCH64 counterpart of commit 1f3b1eb308
, to remove
a pointless check against the memory type of the allocations that the
page tables happened to land in. On ArmV8, we use writeback cacheable
exclusively for all memory.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
This commit is contained in:
parent
748fea6279
commit
d93fe5b579
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@ -497,7 +497,6 @@ ArmConfigureMmu (
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)
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{
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VOID* TranslationTable;
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UINT32 TranslationTableAttribute;
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UINT64 MaxAddress;
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UINTN T0SZ;
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UINTN RootTableEntryCount;
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@ -618,18 +617,7 @@ ArmConfigureMmu (
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RootTableEntryCount * sizeof(UINT64));
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ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
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TranslationTableAttribute = TT_ATTR_INDX_INVALID;
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while (MemoryTable->Length != 0) {
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DEBUG_CODE_BEGIN ();
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// Find the memory attribute for the Translation Table
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if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&
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(UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +
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MemoryTable->Length) {
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TranslationTableAttribute = MemoryTable->Attributes;
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}
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DEBUG_CODE_END ();
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Status = FillTranslationTable (TranslationTable, MemoryTable);
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if (EFI_ERROR (Status)) {
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goto FREE_TRANSLATION_TABLE;
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@ -637,9 +625,6 @@ ArmConfigureMmu (
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MemoryTable++;
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}
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ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ||
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TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK);
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ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
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MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
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MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
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