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ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type check

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This is the AARCH64 counterpart of commit 1f3b1eb3082206e4, to remove
a pointless check against the memory type of the allocations that the
page tables happened to land in. On ArmV8, we use writeback cacheable
exclusively for all memory.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
This commit is contained in:
Ard Biesheuvel 2020-03-07 10:10:07 +01:00 committed by mergify[bot]
parent 748fea6279
commit d93fe5b579
1 changed files with 0 additions and 15 deletions
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15
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
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@ -497,7 +497,6 @@ ArmConfigureMmu (
) )
{ {
VOID* TranslationTable; VOID* TranslationTable;
UINT32 TranslationTableAttribute;
UINT64 MaxAddress; UINT64 MaxAddress;
UINTN T0SZ; UINTN T0SZ;
UINTN RootTableEntryCount; UINTN RootTableEntryCount;
@ -618,18 +617,7 @@ ArmConfigureMmu (
RootTableEntryCount * sizeof(UINT64)); RootTableEntryCount * sizeof(UINT64));
ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
TranslationTableAttribute = TT_ATTR_INDX_INVALID;
while (MemoryTable->Length != 0) { while (MemoryTable->Length != 0) {
DEBUG_CODE_BEGIN ();
// Find the memory attribute for the Translation Table
if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&
(UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +
MemoryTable->Length) {
TranslationTableAttribute = MemoryTable->Attributes;
}
DEBUG_CODE_END ();
Status = FillTranslationTable (TranslationTable, MemoryTable); Status = FillTranslationTable (TranslationTable, MemoryTable);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto FREE_TRANSLATION_TABLE; goto FREE_TRANSLATION_TABLE;
@ -637,9 +625,6 @@ ArmConfigureMmu (
MemoryTable++; MemoryTable++;
} }
ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ||
TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK);
ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT