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UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR. 

Changes includes:
  1. Add new MSR definition:
     1. MSR_XEON_PHI_PPIN_CTL
     2. MSR_XEON_PHI_PPIN
     3. MSR_XEON_PHI_MISC_FEATURE_ENABLES
     4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
  2. Add DisplayModule == 0x85 supports.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Eric Dong 2018-08-30 14:04:38 +08:00
parent c4b073632d
commit dfb208511e
1 changed files with 246 additions and 3 deletions
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249
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
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@ -38,7 +38,8 @@
#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x57 \
DisplayModel == 0x57 || \
DisplayModel == 0x85 \
) \
)
@ -85,9 +86,89 @@ typedef union {
UINT64 Uint64;
} MSR_XEON_PHI_SMI_COUNT_REGISTER;
/**
Package. Protected Processor Inventory Number Enable Control (R/W).
@param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
@endcode
**/
#define MSR_XEON_PHI_PPIN_CTL 0x0000004E
/**
Package. See http://biosbits.org.
MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
/// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
/// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
/// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
/// privileged inventory initialization agent to access MSR_PPIN. After
/// reading MSR_PPIN, the privileged inventory initialization agent should
/// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
/// prevent unauthorized modification to MSR_PPIN_CTL.
///
UINT32 LockOut:1;
///
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
/// Default is 0.
///
UINT32 Enable_PPIN:1;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_PHI_PPIN_CTL_REGISTER;
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
Inventory Number (R/O) A unique value within a given CPUID
family/model/stepping signature that a privileged inventory initialization
agent can access to identify each physical processor, when access to
MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
MSR_PPIN_CTL[bits 1:0] = '10b'.
@param ECX MSR_XEON_PHI_PPIN (0x0000004F)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
@endcode
**/
#define MSR_XEON_PHI_PPIN 0x0000004F
/**
Package. Platform Information Contains power management and other model
specific features enumeration. See http://biosbits.org.
@param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
@param EAX Lower 32-bits of MSR value.
@ -317,6 +398,56 @@ typedef union {
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
/**
Thread. MISC_FEATURE_ENABLES.
@param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
@endcode
**/
#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
/**
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
/// MWAIT instructions do not cause invalid-opcode exceptions when
/// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
/// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
/// other than C0 or C1, the instruction operates as if EAX indicated the
/// C-state C1.
///
UINT32 UserModeMonitorAndMwait:1;
UINT32 Reserved2:30;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;
/**
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
Enhancement. Accessible only while in SMM.
@ -748,6 +879,63 @@ typedef union {
#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
/**
MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] CPL_EQ_0.
///
UINT32 CPL_EQ_0:1;
///
/// [Bit 1] CPL_NEQ_0.
///
UINT32 CPL_NEQ_0:1;
///
/// [Bit 2] JCC.
///
UINT32 JCC:1;
///
/// [Bit 3] NEAR_REL_CALL.
///
UINT32 NEAR_REL_CALL:1;
///
/// [Bit 4] NEAR_IND_CALL.
///
UINT32 NEAR_IND_CALL:1;
///
/// [Bit 5] NEAR_RET.
///
UINT32 NEAR_RET:1;
///
/// [Bit 6] NEAR_IND_JMP.
///
UINT32 NEAR_IND_JMP:1;
///
/// [Bit 7] NEAR_REL_JMP.
///
UINT32 NEAR_REL_JMP:1;
///
/// [Bit 8] FAR_BRANCH.
///
UINT32 FAR_BRANCH:1;
UINT32 Reserved1:23;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_PHI_LBR_SELECT_REGISTER;
/**
Thread. Last Branch Record Stack TOS (R/W).
@ -1212,7 +1400,62 @@ typedef union {
/**
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum
frequency that hardware will select.
@param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
@endcode
**/
#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
/**
MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
/// LLC/Ring.
///
UINT32 MAX_RATIO:7;
UINT32 Reserved1:1;
///
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
/// possible ratio of the LLC/Ring.
///
UINT32 MIN_RATIO:7;
UINT32 Reserved2:17;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;
/**
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
RAPL Domains.".
@param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)