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UefiCpuPkg/Msr: Add CPUID signature check MACROs

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All model-specific MSRs are related to processor signatures that are defined in
each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Jeff Fan 2017-03-07 11:14:35 +08:00
parent 30d995ee08
commit f4c982bf09
20 changed files with 365 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
UefiCpuPkg/Include/Register/Msr/AtomMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,26 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Atom(TM) Processor Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x1C || \
DisplayModel == 0x26 || \
DisplayModel == 0x27 || \
DisplayModel == 0x35 || \
DisplayModel == 0x36 \
) \
)
/** /**
Shared. Model Specific Platform ID (R). Shared. Model Specific Platform ID (R).

21
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,25 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Broadwell microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3D || \
DisplayModel == 0x47 || \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)
/** /**
Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
Facilities.". Facilities.".

19
UefiCpuPkg/Include/Register/Msr/Core2Msr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,23 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Core(TM) 2 Processor Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0F || \
DisplayModel == 0x17 \
) \
)
/** /**
Shared. Model Specific Platform ID (R). Shared. Model Specific Platform ID (R).

18
UefiCpuPkg/Include/Register/Msr/CoreMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel Core Solo and Intel Core Duo Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0E \
) \
)
/** /**
Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2. Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.

18
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel Atom processors based on the Goldmont microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x5C \
) \
)
/** /**
Core. Control Features in Intel 64Processor (R/W). Core. Control Features in Intel 64Processor (R/W).

18
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Haswell-E microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3F \
) \
)
/** /**
Package. Configured State of Enabled Processor Core Count and Logical Package. Configured State of Enabled Processor Core Count and Logical
Processor Count (RO) - After a Power-On RESET, enumerates factory Processor Count (RO) - After a Power-On RESET, enumerates factory

20
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,24 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Haswell microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3C || \
DisplayModel == 0x45 || \
DisplayModel == 0x46 \
) \
)
/** /**
Package. Package.

18
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Ivy Bridge microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3A \
) \
)
/** /**
Package. See http://biosbits.org. Package. See http://biosbits.org.

21
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,25 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Nehalem microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x1A || \
DisplayModel == 0x1E || \
DisplayModel == 0x1F || \
DisplayModel == 0x2E \
) \
)
/** /**
Package. Model Specific Platform ID (R). Package. Model Specific Platform ID (R).

23
UefiCpuPkg/Include/Register/Msr/P6Msr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,27 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is P6 Family Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x03 || \
DisplayModel == 0x05 || \
DisplayModel == 0x07 || \
DisplayModel == 0x08 || \
DisplayModel == 0x0A || \
DisplayModel == 0x0B \
) \
)
/** /**
See Section 35.22, "MSRs in Pentium Processors.". See Section 35.22, "MSRs in Pentium Processors.".

15
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,19 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Pentium(R) 4 Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x0F \
)
/** /**
3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
Determination.". Determination.".

18
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Pentium M Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0D \
) \
)
/** /**
See Section 35.22, "MSRs in Pentium Processors.". See Section 35.22, "MSRs in Pentium Processors.".

20
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,24 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Pentium Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x05 && \
( \
DisplayModel == 0x01 || \
DisplayModel == 0x02 || \
DisplayModel == 0x04 \
) \
)
/** /**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.". See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".

19
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,23 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Sandy Bridge microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x2A || \
DisplayModel == 0x2D \
) \
)
/** /**
Thread. SMI Counter (R/O). Thread. SMI Counter (R/O).

22
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,26 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Silvermont microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x37 || \
DisplayModel == 0x4A || \
DisplayModel == 0x4D || \
DisplayModel == 0x5A || \
DisplayModel == 0x5D \
) \
)
/** /**
Module. Model Specific Platform ID (R). Module. Model Specific Platform ID (R).

19
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,23 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel processors based on the Skylake microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x4E || \
DisplayModel == 0x5E \
) \
)
/** /**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1. RW if MSR_PLATFORM_INFO.[28] = 1.

19
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,23 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor Series 5600?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x25 || \
DisplayModel == 0x2C \
) \
)
/** /**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR. handler to handle unsuccessful read of this MSR.

19
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,23 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor D product Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)
/** /**
Package. Protected Processor Inventory Number Enable Control (R/W). Package. Protected Processor Inventory Number Enable Control (R/W).

18
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor E7 Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x2F \
) \
)
/** /**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR. handler to handle unsuccessful read of this MSR.

18
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR. provided for that MSR.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -26,6 +26,22 @@
#include <Register/ArchitecturalMsr.h> #include <Register/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Phi(TM) processor Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x57 \
) \
)
/** /**
Thread. SMI Counter (R/O). Thread. SMI Counter (R/O).