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ARM Packages: Rename PcdNormal* into Pcd* PCDs 

The denomination 'Normal' was used to make reference to the 'Normal'
or 'Non Secure' or 'Non Trusted' world.
To avoid confusion, this prefix has been removed from PCDs to define
the normal world.

The PCDs explicitely related to the Secure/Trusted World continue to
have the 'Sec' prefix.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12416 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-22 23:06:31 +00:00
parent 2dbcb8f0a3
commit f92b93c9a3
32 changed files with 84 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
ArmPkg/ArmPkg.dec
View File

@ -86,10 +86,10 @@
#
# ARM Normal (or Non Secure) Firmware PCDs
#
gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0|UINT32|0x0000002B
gArmTokenSpaceGuid.PcdNormalFdSize|0|UINT32|0x0000002C
gArmTokenSpaceGuid.PcdNormalFvBaseAddress|0|UINT32|0x0000002D
gArmTokenSpaceGuid.PcdNormalFvSize|0|UINT32|0x0000002E
gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
# System Memory (DRAM): These PCDs define the region of in-built system memory
# Some platforms can get DRAM extensions, these additional regions will be declared

4
ArmPkg/Library/DebugAgentSymbolsOnlyLib/DebugAgentSymbolsOnlyLib.c
View File

@ -293,7 +293,7 @@ InitializeDebugAgent (
//
// Get the PrePi or PrePeiCore module (defined as SEC type module)
//
Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)PcdGet32(PcdNormalFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)PcdGet32(PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
if (!EFI_ERROR(Status)) {
Status = GetImageContext (FfsHeader,&ImageContext);
if (!EFI_ERROR(Status)) {
@ -304,7 +304,7 @@ InitializeDebugAgent (
//
// Get the PeiCore module (defined as PEI_CORE type module)
//
Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)PcdGet32(PcdNormalFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);
Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)PcdGet32(PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);
if (!EFI_ERROR(Status)) {
Status = GetImageContext (FfsHeader,&ImageContext);
if (!EFI_ERROR(Status)) {

2
ArmPkg/Library/DebugAgentSymbolsOnlyLib/DebugAgentSymbolsOnlyLib.inf
View File

@ -35,4 +35,4 @@
[Pcd]
gArmTokenSpaceGuid.PcdSecureFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdFvBaseAddress

6
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-MPCore.fdf
View File

@ -27,8 +27,8 @@
[FD.ArmRealViewEb_EFI]
BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress
Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize
BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdFdBaseAddress
Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize
ErasePolarity = 1
BlockSize = 0x00010000
NumBlocks = 0x20
@ -54,7 +54,7 @@ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
FV = FVMAIN_SEC
0x00050000|0x00100000
gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
################################################################################

6
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-UniCore.fdf
View File

@ -27,8 +27,8 @@
[FD.ArmRealViewEb_EFI]
BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress
Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize
BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdFdBaseAddress
Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize
ErasePolarity = 1
BlockSize = 0x00010000
NumBlocks = 0x20
@ -54,7 +54,7 @@ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
FV = FVMAIN_SEC
0x00050000|0x00100000
gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
################################################################################

2
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSec.c
View File

@ -65,5 +65,5 @@ ArmPlatformSecExtraAction (
OUT UINTN* JumpAddress
)
{
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
*JumpAddress = PcdGet32(PcdFvBaseAddress);
}

2
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf
View File

@ -40,4 +40,4 @@
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdFvBaseAddress

8
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
View File

@ -55,11 +55,11 @@ FV = FVMAIN_SEC
[FD.ArmVExpress_EFI]
!if $(EDK2_ARMVE_STANDALONE) == 1
BaseAddress = 0x45000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the Firmware in NOR Flash.
BaseAddress = 0x45000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
!else
BaseAddress = 0x80000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the Firmware in remapped DRAM.
BaseAddress = 0x80000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM.
!endif
Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize # The size in bytes of the FLASH Device
Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
# This one is tricky, it must be: BlockSize * NumBlocks = Size
@ -83,7 +83,7 @@ NumBlocks = 0x200
################################################################################
0x00000000|0x00200000
gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvBaseSize
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvBaseSize
FV = FVMAIN_COMPACT

4
ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
View File

@ -15,8 +15,8 @@ PCDs Description :
# Firmware Device / Volume
gArmTokenSpaceGuid.PcdSecureFdBaseAddress : Base address of your Secure Firmware Device
gArmTokenSpaceGuid.PcdSecureFdSize : Size in byte of your Secure Firmware Device.
gArmTokenSpaceGuid.PcdNormalFdBaseAddress : Base Address of your Non-Secure/Normal World Firmware Device.
gArmTokenSpaceGuid.PcdNormalFdSize : Size in bytes of your Non-Secure/Normal World Firmware Device
gArmTokenSpaceGuid.PcdFdBaseAddress : Base Address of your Non-Secure/Normal World Firmware Device.
gArmTokenSpaceGuid.PcdFdSize : Size in bytes of your Non-Secure/Normal World Firmware Device
# Stacks
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase : Base of Secure Stack for Secure World

10
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
View File

@ -33,7 +33,7 @@ NonSecureWaitForFirmware (
VOID (*secondary_start)(VOID);
// The secondary cores will execute the firmware once wake from WFI.
secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress);
ArmCallWFI();
@ -65,7 +65,7 @@ ArmPlatformSecExtraAction (
if (FeaturePcdGet (PcdStandalone) == FALSE) {
if (IS_PRIMARY_CORE(MpId)) {
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
UINTN* StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);
// Patch the DRAM to make an infinite loop at the start address
*StartAddress = 0xEAFFFFFE; // opcode for while(1)
@ -73,7 +73,7 @@ ArmPlatformSecExtraAction (
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
*JumpAddress = PcdGet32(PcdFvBaseAddress);
} else {
// When the primary core is stopped by the hardware debugger to copy the firmware
// into DRAM. The secondary cores are still running. As soon as the first bytes of
@ -90,7 +90,7 @@ ArmPlatformSecExtraAction (
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
// To enter into Non Secure state, we need to make a return from exception
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
*JumpAddress = PcdGet32(PcdFvBaseAddress);
} else {
// We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
// cores would make crash the system by setting their stacks in DRAM before the primary core has not
@ -98,6 +98,6 @@ ArmPlatformSecExtraAction (
*JumpAddress = (UINTN)NonSecureWaitForFirmware;
}
} else {
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
*JumpAddress = PcdGet32(PcdFvBaseAddress);
}
}

2
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
View File

@ -45,7 +45,7 @@
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

22
ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c
View File

@ -100,47 +100,47 @@ MemoryPeim (
);
SystemMemoryTop = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);
FdTop = PcdGet32(PcdNormalFdBaseAddress) + PcdGet32(PcdNormalFdSize);
FdTop = PcdGet32(PcdFdBaseAddress) + PcdGet32(PcdFdSize);
// EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
// core to overwrite this area we must mark the region with the attribute non-present
if ((PcdGet32 (PcdNormalFdBaseAddress) >= PcdGet32 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {
if ((PcdGet32 (PcdFdBaseAddress) >= PcdGet32 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {
Found = FALSE;
// Search for System Memory Hob that contains the firmware
NextHob.Raw = GetHobList ();
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
(PcdGet32(PcdNormalFdBaseAddress) >= NextHob.ResourceDescriptor->PhysicalStart) &&
(PcdGet32(PcdFdBaseAddress) >= NextHob.ResourceDescriptor->PhysicalStart) &&
(FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
{
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
if (PcdGet32(PcdNormalFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {
if (PcdGet32(PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {
if (SystemMemoryTop == FdTop) {
NextHob.ResourceDescriptor->ResourceAttribute = ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT;
} else {
// Create the System Memory HOB for the firmware with the non-present attribute
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,
PcdGet32(PcdNormalFdBaseAddress),
PcdGet32(PcdNormalFdSize));
PcdGet32(PcdFdBaseAddress),
PcdGet32(PcdFdSize));
// Top of the FD is system memory available for UEFI
NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdNormalFdSize);
NextHob.ResourceDescriptor->ResourceLength -= PcdGet32(PcdNormalFdSize);
NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdFdSize);
NextHob.ResourceDescriptor->ResourceLength -= PcdGet32(PcdFdSize);
}
} else {
// Create the System Memory HOB for the firmware with the non-present attribute
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,
PcdGet32(PcdNormalFdBaseAddress),
PcdGet32(PcdNormalFdSize));
PcdGet32(PcdFdBaseAddress),
PcdGet32(PcdFdSize));
// Update the HOB
NextHob.ResourceDescriptor->ResourceLength = PcdGet32(PcdNormalFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;
NextHob.ResourceDescriptor->ResourceLength = PcdGet32(PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;
// If there is some memory available on the top of the FD then create a HOB
if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) {

4
ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
View File

@ -45,8 +45,8 @@
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize

4
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c
View File

@ -108,8 +108,8 @@ InitializeMemory (
SystemMemoryBase = (UINTN)FixedPcdGet32 (PcdSystemMemoryBase);
SystemMemoryTop = SystemMemoryBase + (UINTN)FixedPcdGet32 (PcdSystemMemorySize);
FdBase = (UINTN)PcdGet32 (PcdNormalFdBaseAddress);
FdTop = FdBase + (UINTN)PcdGet32 (PcdNormalFdSize);
FdBase = (UINTN)PcdGet32 (PcdFdBaseAddress);
FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
//
// Initialize the System Memory (DRAM)

4
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
View File

@ -52,8 +52,8 @@
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize

2
ArmPlatformPkg/PlatformPei/PlatformPeiLib.c
View File

@ -29,7 +29,7 @@ PlatformPeim (
BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));
BuildFvHob (PcdGet32(PcdNormalFvBaseAddress), PcdGet32(PcdNormalFvSize));
BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));
return EFI_SUCCESS;
}

8
ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
View File

@ -40,11 +40,11 @@
gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize

8
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
View File

@ -49,11 +49,11 @@
gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize

4
ArmPlatformPkg/PrePeiCore/MainMPCore.c
View File

@ -80,8 +80,8 @@ PrimaryMain (
// Note also: HOBs (pei temp ram) MUST be above stack
//
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)
SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);
SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));

4
ArmPlatformPkg/PrePeiCore/MainUniCore.c
View File

@ -42,8 +42,8 @@ PrimaryMain (
// Note also: HOBs (pei temp ram) MUST be above stack
//
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)
SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);
SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
View File

@ -76,7 +76,7 @@ _InitGlobals:
_PrepareArguments:
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)
add r2, r2, #4
ldr r1, [r2]

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
View File

@ -78,7 +78,7 @@ _InitGlobals
_PrepareArguments
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)
add r2, r2, #4
ldr r1, [r2]

4
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
View File

@ -55,8 +55,8 @@
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

4
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
View File

@ -53,8 +53,8 @@
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

6
ArmPlatformPkg/PrePi/ModuleEntryPoint.S
View File

@ -48,9 +48,9 @@ _SetupStackPosition:
add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize
// Calculate Top of the Firmware Device
LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
LoadConstantToReg (FixedPcdGet32(PcdNormalFdSize), r3)
add r3, r3, r2 // r4 = FdTop = PcdNormalFdBaseAddress + PcdNormalFdSize
LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)
LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)
add r3, r3, r2 // r4 = FdTop = PcdFdBaseAddress + PcdFdSize
// UEFI Memory Size (stacks are allocated in this region)
LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)

6
ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
View File

@ -49,9 +49,9 @@ _SetupStackPosition
add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize
// Calculate Top of the Firmware Device
LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
LoadConstantToReg (FixedPcdGet32(PcdNormalFdSize), r3)
add r3, r3, r2 // r4 = FdTop = PcdNormalFdBaseAddress + PcdNormalFdSize
LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)
LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)
add r3, r3, r2 // r4 = FdTop = PcdFdBaseAddress + PcdFdSize
// UEFI Memory Size (stacks are allocated in this region)
LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)

8
ArmPlatformPkg/PrePi/PeiMPCore.inf
View File

@ -64,11 +64,11 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdVFPEnabled
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize

8
ArmPlatformPkg/PrePi/PeiUniCore.inf
View File

@ -62,11 +62,11 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdVFPEnabled
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize

2
ArmPlatformPkg/Sec/Sec.c
View File

@ -207,7 +207,7 @@ CEntryPoint (
copy_cpsr_into_spsr ();
}
JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
JumpAddress = PcdGet32 (PcdFvBaseAddress);
ArmPlatformSecExtraAction (MpId, &JumpAddress);
return_from_exception (JumpAddress);

2
ArmPlatformPkg/Sec/Sec.inf
View File

@ -56,7 +56,7 @@
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize

6
BeagleBoardPkg/BeagleBoardPkg-next.fdf
View File

@ -27,8 +27,8 @@
[FD.BeagleBoard_EFI]
BaseAddress = 0x80008000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress #The base address of the FLASH Device.
Size = 0x00080000|gArmTokenSpaceGuid.PcdNormalFdSize #The size in bytes of the FLASH Device
BaseAddress = 0x80008000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
Size = 0x00080000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
BlockSize = 0x1
NumBlocks = 0x80000
@ -56,7 +56,7 @@ NumBlocks = 0x80000
0x00000208|0x0007FDF8
!endif
gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvBaseSize
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvBaseSize
FV = FVMAIN_COMPACT
################################################################################

4
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardLib.inf
View File

@ -48,8 +48,8 @@
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFdBaseAddress
gArmTokenSpaceGuid.PcdNormalFdSize
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize