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ArmPkg: Ensured the stack is always quad-word aligned 

From the AArch64 Procedure Call Standard (ARM IHI 0055B):

  5.2.2.1 Universal stack constraints
  At all times the following basic constraints must hold:
  - SP mod 16 = 0. The stack must be quad-word aligned.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-11-11 00:51:11 +00:00 committed by oliviermartin
parent 6382e5df4e
commit fb7ea6114a
3 changed files with 12 additions and 12 deletions
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8
ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S
View File

@ -18,8 +18,8 @@
GCC_ASM_EXPORT(ArmCallHvc)
ASM_PFX(ArmCallHvc):
// Push x0 on the stack
str x0, [sp, #-8]!
// Push x0 on the stack - The stack must always be quad-word aligned
str x0, [sp, #-16]!
// Load the HVC arguments values into the appropriate registers
ldp x6, x7, [x0, #48]
@ -30,9 +30,9 @@ ASM_PFX(ArmCallHvc):
hvc #0
// Pop the ARM_HVC_ARGS structure address from the stack into x9
ldr x9, [sp], #8
ldr x9, [sp], #16
// Store the HVC returned values into the appropriate registers
// Store the HVC returned values into the ARM_HVC_ARGS structure.
// A HVC call can return up to 4 values
stp x2, x3, [x9, #16]
stp x0, x1, [x9, #0]

8
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
View File

@ -313,8 +313,8 @@ ASM_PFX(ArmDisableBranchPrediction):
ASM_PFX(AArch64AllDataCachesOperation):
// We can use regs 0-7 and 9-15 without having to save/restore.
// Save our link register on the stack.
str x30, [sp, #-0x10]!
// Save our link register on the stack. - The stack must always be quad-word aligned
str x30, [sp, #-16]!
mov x1, x0 // Save Function call in x1
mrs x6, clidr_el1 // Read EL1 CLIDR
and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)
@ -326,8 +326,8 @@ ASM_PFX(AArch64AllDataCachesOperation):
ASM_PFX(AArch64PerformPoUDataCacheOperation):
// We can use regs 0-7 and 9-15 without having to save/restore.
// Save our link register on the stack.
str x30, [sp, #-0x10]!
// Save our link register on the stack. - The stack must always be quad-word aligned
str x30, [sp, #-16]!
mov x1, x0 // Save Function call in x1
mrs x6, clidr_el1 // Read EL1 CLIDR
and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)

8
ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
View File

@ -17,8 +17,8 @@
GCC_ASM_EXPORT(ArmCallSmc)
ASM_PFX(ArmCallSmc):
// Push x0 on the stack
str x0, [sp, #-8]!
// Push x0 on the stack - The stack must always be quad-word aligned
str x0, [sp, #-16]!
// Load the SMC arguments values into the appropriate registers
ldp x6, x7, [x0, #48]
@ -29,9 +29,9 @@ ASM_PFX(ArmCallSmc):
smc #0
// Pop the ARM_SMC_ARGS structure address from the stack into x9
ldr x9, [sp], #8
ldr x9, [sp], #16
// Store the SMC returned values into the appropriate registers
// Store the SMC returned values into the ARM_SMC_ARGS structure.
// A SMC call can return up to 4 values - we do not need to store back x4-x7.
stp x2, x3, [x9, #16]
stp x0, x1, [x9, #0]