mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/PciBus: Correct typos
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Ray Ni
parent
1f6785c4b7
commit
fcdfcdbfc2
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@ -1,7 +1,7 @@
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/** @file
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PCI command register operations supporting functions implementation for PCI Bus module.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -75,12 +75,12 @@ PciOperateRegister (
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}
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/**
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Check the cpability supporting by given device.
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Check the capability supporting by given device.
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@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
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@retval TRUE Cpability supportted.
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@retval FALSE Cpability not supportted.
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@retval TRUE Capability supported.
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@retval FALSE Capability not supported.
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**/
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BOOLEAN
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@ -103,7 +103,7 @@ PciCapabilitySupport (
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@param Offset A pointer to the offset returned.
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@param NextRegBlock A pointer to the next block returned.
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@retval EFI_SUCCESS Successfuly located capability register block.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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@ -121,7 +121,7 @@ LocateCapabilityRegBlock (
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UINT8 CapabilityID;
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//
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// To check the cpability of this device supports
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// To check the capability of this device supports
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//
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if (!PciCapabilitySupport (PciIoDevice)) {
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return EFI_UNSUPPORTED;
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@ -195,7 +195,7 @@ LocateCapabilityRegBlock (
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@param Offset A pointer to the offset returned.
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@param NextRegBlock A pointer to the next block returned.
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@retval EFI_SUCCESS Successfuly located capability register block.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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@ -1,7 +1,7 @@
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/** @file
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PCI command register operations supporting functions declaration for PCI Bus module.
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Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -84,12 +84,12 @@ PciOperateRegister (
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);
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/**
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Check the cpability supporting by given device.
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Check the capability supporting by given device.
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@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
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@retval TRUE Cpability supportted.
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@retval FALSE Cpability not supportted.
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@retval TRUE Capability supported.
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@retval FALSE Capability not supported.
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**/
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BOOLEAN
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@ -105,7 +105,7 @@ PciCapabilitySupport (
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@param Offset A pointer to the offset returned.
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@param NextRegBlock A pointer to the next block returned.
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@retval EFI_SUCCESS Successfuly located capability register block.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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@ -126,7 +126,7 @@ LocateCapabilityRegBlock (
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@param Offset A pointer to the offset returned.
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@param NextRegBlock A pointer to the next block returned.
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@retval EFI_SUCCESS Successfuly located capability register block.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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@ -176,7 +176,7 @@ LocatePciExpressCapabilityRegBlock (
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PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
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/**
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Macro that disalbes command register.
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Macro that disables command register.
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@param a[in] Pointer to instance of PCI_IO_DEVICE.
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@param b[in] The disabled value written into command register.
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@ -224,7 +224,7 @@ LocatePciExpressCapabilityRegBlock (
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PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
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/**
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Macro that disalbes PCI bridge control register.
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Macro that disables PCI bridge control register.
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@param a[in] Pointer to instance of PCI_IO_DEVICE.
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@param b[in] The disabled value written into command register.
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@ -1,5 +1,5 @@
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/** @file
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Supporting functions implementaion for PCI devices management.
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Supporting functions implementation for PCI devices management.
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2018 Hewlett Packard Enterprise Development LP<BR>
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@ -66,7 +66,7 @@ InsertPciDevice (
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}
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/**
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Destroy root bridge and remove it from deivce tree.
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Destroy root bridge and remove it from device tree.
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@param RootBridge The bridge want to be removed.
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@ -86,7 +86,7 @@ DestroyRootBridge (
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All direct or indirect allocated resource for this node will be freed.
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@param PciIoDevice A pointer to the PCI_IO_DEVICE to be destoried.
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@param PciIoDevice A pointer to the PCI_IO_DEVICE to be destroyed.
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**/
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VOID
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@ -155,7 +155,7 @@ DestroyPciDeviceTree (
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@param Controller Root bridge handle.
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@retval EFI_SUCCESS Destory all devcie nodes successfully.
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@retval EFI_SUCCESS Destroy all device nodes successfully.
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@retval EFI_NOT_FOUND Cannot find any PCI device under specified
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root bridge.
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@ -824,7 +824,7 @@ StartPciDevices (
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/**
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Create root bridge device.
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@param RootBridgeHandle Specified root bridge hanle.
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@param RootBridgeHandle Specified root bridge handle.
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@return The crated root bridge device instance, NULL means no
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root bridge device instance created.
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@ -937,9 +937,9 @@ GetRootBridgeByHandle (
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}
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/**
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Judege whether Pci device existed.
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Judge whether Pci device existed.
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@param Bridge Parent bridege instance.
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@param Bridge Parent bridge instance.
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@param PciIoDevice Device instance.
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@retval TRUE Pci device existed.
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@ -1,7 +1,7 @@
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/** @file
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Supporting functions declaration for PCI devices management.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -50,7 +50,7 @@ InsertPciDevice (
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);
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/**
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Destroy root bridge and remove it from deivce tree.
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Destroy root bridge and remove it from device tree.
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@param RootBridge The bridge want to be removed.
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@ -80,7 +80,7 @@ DestroyPciDeviceTree (
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@param Controller Root bridge handle.
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@retval EFI_SUCCESS Destory all devcie nodes successfully.
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@retval EFI_SUCCESS Destroy all device nodes successfully.
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@retval EFI_NOT_FOUND Cannot find any PCI device under specified
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root bridge.
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@ -187,7 +187,7 @@ StartPciDevices (
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/**
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Create root bridge device.
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@param RootBridgeHandle Specified root bridge hanle.
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@param RootBridgeHandle Specified root bridge handle.
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@return The crated root bridge device instance, NULL means no
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root bridge device instance created.
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@ -214,9 +214,9 @@ GetRootBridgeByHandle (
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/**
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Judege whether Pci device existed.
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Judge whether Pci device existed.
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@param Bridge Parent bridege instance.
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@param Bridge Parent bridge instance.
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@param PciIoDevice Device instance.
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@retval TRUE Pci device existed.
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@ -261,7 +261,7 @@ LocateVgaDevice (
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All direct or indirect allocated resource for this node will be freed.
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@param PciIoDevice A pointer to the PCI_IO_DEVICE to be destoried.
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@param PciIoDevice A pointer to the PCI_IO_DEVICE to be destroyed.
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**/
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VOID
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@ -1,7 +1,7 @@
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/** @file
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Functions implementation for Bus Specific Driver Override protoocl.
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Functions implementation for Bus Specific Driver Override protocol.
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Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -1,7 +1,7 @@
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/** @file
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Functions declaration for Bus Specific Driver Override protoocl.
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Functions declaration for Bus Specific Driver Override protocol.
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Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -442,8 +442,8 @@ NotifyPhase (
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@retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
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EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
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@retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
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not enumerate this device, including its child devices if it is a PCI-to-PCI
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bridge.
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not enumerate this device, including its child devices if it is a PCI-to-PCI
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bridge.
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**/
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EFI_STATUS
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@ -1,7 +1,7 @@
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/** @file
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PCI emumeration support functions implementation for PCI Bus module.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -88,7 +88,7 @@ PciDevicePresent (
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root bridge will then be created.
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@param Bridge Parent bridge instance.
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@param StartBusNumber Bus number of begining.
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@param StartBusNumber Bus number of beginning.
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@retval EFI_SUCCESS PCI device is found.
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@retval other Some error occurred when reading PCI bridge information.
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@ -208,7 +208,7 @@ PciPciDeviceInfoCollector (
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}
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/**
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Seach required device and create PCI device instance.
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Search required device and create PCI device instance.
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@param Bridge Parent bridge instance.
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@param Pci Input PCI device information block.
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@ -370,14 +370,14 @@ DumpPpbPaddingResource (
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if (Descriptor->AddrSpaceGranularity == 32) {
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//
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// prefechable
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// prefetchable
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//
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if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {
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Type = PciBarTypePMem32;
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}
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//
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// Non-prefechable
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// Non-prefetchable
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//
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if (Descriptor->SpecificFlag == 0) {
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Type = PciBarTypeMem32;
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@ -386,14 +386,14 @@ DumpPpbPaddingResource (
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if (Descriptor->AddrSpaceGranularity == 64) {
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//
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// prefechable
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// prefetchable
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//
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if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {
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Type = PciBarTypePMem64;
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}
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//
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// Non-prefechable
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// Non-prefetchable
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//
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if (Descriptor->SpecificFlag == 0) {
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Type = PciBarTypeMem64;
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@ -568,7 +568,7 @@ GatherPpbInfo (
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PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
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//
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// Initalize the bridge control register
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// Initialize the bridge control register
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//
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PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
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@ -722,7 +722,7 @@ GatherP2CInfo (
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PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
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//
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// Initalize the bridge control register
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// Initialize the bridge control register
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//
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PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);
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}
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@ -746,7 +746,7 @@ GatherP2CInfo (
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}
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/**
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Create device path for pci deivce.
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Create device path for pci device.
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@param ParentDevicePath Parent bridge's path.
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@param PciIoDevice Pci device instance.
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@ -922,7 +922,7 @@ BarExisted (
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@param PciIoDevice Pci device instance.
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@param Command Input command register value, and
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returned supported register value.
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@param BridgeControl Inout bridge control value for PPB or P2C, and
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@param BridgeControl Input bridge control value for PPB or P2C, and
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returned supported bridge control value.
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@param OldCommand Returned and stored old command register offset.
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@param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
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@ -1205,7 +1205,7 @@ DetermineDeviceAttribute (
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EFI_STATUS Status;
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//
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// For Root Bridge, just copy it by RootBridgeIo proctocol
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// For Root Bridge, just copy it by RootBridgeIo protocol
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// so as to keep consistent with the actual attribute
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//
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if (PciIoDevice->Parent == NULL) {
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@ -1282,7 +1282,7 @@ DetermineDeviceAttribute (
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return Status;
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}
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//
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// Detect Fast Bact to Bact support for the device under the bridge
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// Detect Fast Back to Back support for the device under the bridge
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//
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Status = GetFastBackToBackSupport (Temp, PCI_PRIMARY_STATUS_OFFSET);
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if (FastB2BSupport && EFI_ERROR (Status)) {
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@ -1695,7 +1695,7 @@ PciIovParseVfBar (
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}
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//
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// Fix the length to support some spefic 64 bit BAR
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// Fix the length to support some special 64 bit BAR
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//
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Value |= ((UINT32) -1 << HighBitSet32 (Value));
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@ -1822,7 +1822,7 @@ PciParseBar (
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}
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//
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// Workaround. Some platforms inplement IO bar with 0 length
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// Workaround. Some platforms implement IO bar with 0 length
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// Need to treat it as no-bar
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//
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if (PciIoDevice->PciBar[BarIndex].Length == 0) {
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@ -1906,7 +1906,7 @@ PciParseBar (
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}
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//
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// Fix the length to support some spefic 64 bit BAR
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// Fix the length to support some special 64 bit BAR
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//
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if (Value == 0) {
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DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
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@ -1987,7 +1987,7 @@ InitializePciDevice (
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//
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// Put all the resource apertures
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// Resource base is set to all ones so as to indicate its resource
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// has not been alloacted
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// has not been allocated
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//
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for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
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@ -2077,10 +2077,10 @@ InitializeP2C (
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}
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/**
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Create and initiliaze general PCI I/O device instance for
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Create and initialize general PCI I/O device instance for
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PCI device/bridge device/hotplug bridge device.
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@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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@param Bridge Parent bridge instance.
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@param Pci Input Pci information block.
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@param Bus Device Bus NO.
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@param Device Device device NO.
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@ -2443,7 +2443,7 @@ PciEnumeratorLight (
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}
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//
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// Record the root bridgeio protocol
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// Record the root bridge-io protocol
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//
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RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
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@ -2476,7 +2476,7 @@ PciEnumeratorLight (
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} else {
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//
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// If unsuccessly, destroy the entire node
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// If unsuccessfully, destroy the entire node
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//
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DestroyRootBridge (RootBridgeDev);
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}
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|
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@ -1,7 +1,7 @@
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/** @file
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PCI emumeration support functions declaration for PCI Bus module.
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PCI enumeration support functions declaration for PCI Bus module.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
|
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
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|
|
@ -44,7 +44,7 @@ PciDevicePresent (
|
|||
root bridge will then be created.
|
||||
|
||||
@param Bridge Parent bridge instance.
|
||||
@param StartBusNumber Bus number of begining.
|
||||
@param StartBusNumber Bus number of beginning.
|
||||
|
||||
@retval EFI_SUCCESS PCI device is found.
|
||||
@retval other Some error occurred when reading PCI bridge information.
|
||||
|
|
@ -57,7 +57,7 @@ PciPciDeviceInfoCollector (
|
|||
);
|
||||
|
||||
/**
|
||||
Seach required device and create PCI device instance.
|
||||
Search required device and create PCI device instance.
|
||||
|
||||
@param Bridge Parent bridge instance.
|
||||
@param Pci Input PCI device information block.
|
||||
|
|
@ -144,12 +144,12 @@ GatherP2CInfo (
|
|||
);
|
||||
|
||||
/**
|
||||
Create device path for pci deivce.
|
||||
Create device path for pci device.
|
||||
|
||||
@param ParentDevicePath Parent bridge's path.
|
||||
@param PciIoDevice Pci device instance.
|
||||
|
||||
@return device path protocol instance for specific pci device.
|
||||
@return Device path protocol instance for specific pci device.
|
||||
|
||||
**/
|
||||
EFI_DEVICE_PATH_PROTOCOL *
|
||||
|
|
@ -204,7 +204,7 @@ BarExisted (
|
|||
@param PciIoDevice Pci device instance.
|
||||
@param Command Input command register value, and
|
||||
returned supported register value.
|
||||
@param BridgeControl Inout bridge control value for PPB or P2C, and
|
||||
@param BridgeControl Input bridge control value for PPB or P2C, and
|
||||
returned supported bridge control value.
|
||||
@param OldCommand Returned and stored old command register offset.
|
||||
@param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
|
||||
|
|
@ -361,7 +361,7 @@ InitializeP2C (
|
|||
);
|
||||
|
||||
/**
|
||||
Create and initiliaze general PCI I/O device instance for
|
||||
Create and initialize general PCI I/O device instance for
|
||||
PCI device/bridge device/hotplug bridge device.
|
||||
|
||||
@param Bridge Parent bridge instance.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PCI Hot Plug support functions implementation for PCI Bus module..
|
||||
|
||||
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -41,7 +41,7 @@ PciHPCInitialized (
|
|||
}
|
||||
|
||||
/**
|
||||
Compare two device pathes to check if they are exactly same.
|
||||
Compare two device paths to check if they are exactly same.
|
||||
|
||||
@param DevicePath1 A pointer to the first device path data structure.
|
||||
@param DevicePath2 A pointer to the second device path data structure.
|
||||
|
|
@ -81,7 +81,7 @@ EfiCompareDevicePath (
|
|||
private data structure.
|
||||
|
||||
@retval EFI_SUCCESS They are same.
|
||||
@retval EFI_UNSUPPORTED No PCI Hot Plug controler on the platform.
|
||||
@retval EFI_UNSUPPORTED No PCI Hot Plug controller on the platform.
|
||||
@retval EFI_OUT_OF_RESOURCES No memory to constructor root hot plug private
|
||||
data structure.
|
||||
|
||||
|
|
@ -137,7 +137,7 @@ InitializeHotPlugSupport (
|
|||
|
||||
@param HpbDevicePath A pointer to device path data structure to be tested.
|
||||
@param HpIndex If HpIndex is not NULL, return the index of root hot
|
||||
plug in global array when TRUE is retuned.
|
||||
plug in global array when TRUE is returned.
|
||||
|
||||
@retval TRUE The device path is for root pci hot plug bus.
|
||||
@retval FALSE The device path is not for root pci hot plug bus.
|
||||
|
|
@ -171,7 +171,7 @@ IsRootPciHotPlugBus (
|
|||
|
||||
@param HpcDevicePath A pointer to device path data structure to be tested.
|
||||
@param HpIndex If HpIndex is not NULL, return the index of root hot
|
||||
plug in global array when TRUE is retuned.
|
||||
plug in global array when TRUE is returned.
|
||||
|
||||
@retval TRUE The device path is for root pci hot plug controller.
|
||||
@retval FALSE The device path is not for root pci hot plug controller.
|
||||
|
|
@ -204,9 +204,9 @@ IsRootPciHotPlugController (
|
|||
Creating event object for PCI Hot Plug controller.
|
||||
|
||||
@param HpIndex Index of hot plug device in global array.
|
||||
@param Event The retuned event that invoke this function.
|
||||
@param Event The returned event that invoke this function.
|
||||
|
||||
@return Status of create event invoken.
|
||||
@return Status of create event.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
|
|
@ -328,7 +328,7 @@ IsSHPC (
|
|||
|
||||
@param[in] PciIoDevice The device being checked.
|
||||
|
||||
@retval TRUE PciIoDevice is a PCIe port that accepts a hotplugged device.
|
||||
@retval TRUE PciIoDevice is a PCIe port that accepts a hot-plugged device.
|
||||
@retval FALSE Otherwise.
|
||||
|
||||
**/
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PCI Hot Plug support functions declaration for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -31,7 +31,7 @@ typedef struct {
|
|||
} ROOT_HPC_DATA;
|
||||
|
||||
//
|
||||
// Reference of some global variabes
|
||||
// Reference of some global variables
|
||||
//
|
||||
extern EFI_PCI_HOT_PLUG_INIT_PROTOCOL *gPciHotPlugInit;
|
||||
extern EFI_HPC_LOCATION *gPciRootHpcPool;
|
||||
|
|
@ -52,7 +52,7 @@ PciHPCInitialized (
|
|||
);
|
||||
|
||||
/**
|
||||
Compare two device pathes to check if they are exactly same.
|
||||
Compare two device paths to check if they are exactly same.
|
||||
|
||||
@param DevicePath1 A pointer to the first device path data structure.
|
||||
@param DevicePath2 A pointer to the second device path data structure.
|
||||
|
|
@ -75,7 +75,7 @@ EfiCompareDevicePath (
|
|||
private data structure.
|
||||
|
||||
@retval EFI_SUCCESS They are same.
|
||||
@retval EFI_UNSUPPORTED No PCI Hot Plug controler on the platform.
|
||||
@retval EFI_UNSUPPORTED No PCI Hot Plug controller on the platform.
|
||||
@retval EFI_OUT_OF_RESOURCES No memory to constructor root hot plug private
|
||||
data structure.
|
||||
|
||||
|
|
@ -104,7 +104,7 @@ IsPciHotPlugBus (
|
|||
|
||||
@param HpbDevicePath A pointer to device path data structure to be tested.
|
||||
@param HpIndex If HpIndex is not NULL, return the index of root hot
|
||||
plug in global array when TRUE is retuned.
|
||||
plug in global array when TRUE is returned.
|
||||
|
||||
@retval TRUE The device path is for root pci hot plug bus.
|
||||
@retval FALSE The device path is not for root pci hot plug bus.
|
||||
|
|
@ -121,7 +121,7 @@ IsRootPciHotPlugBus (
|
|||
|
||||
@param HpcDevicePath A pointer to device path data structure to be tested.
|
||||
@param HpIndex If HpIndex is not NULL, return the index of root hot
|
||||
plug in global array when TRUE is retuned.
|
||||
plug in global array when TRUE is returned.
|
||||
|
||||
@retval TRUE The device path is for root pci hot plug controller.
|
||||
@retval FALSE The device path is not for root pci hot plug controller.
|
||||
|
|
@ -137,9 +137,9 @@ IsRootPciHotPlugController (
|
|||
Creating event object for PCI Hot Plug controller.
|
||||
|
||||
@param HpIndex Index of hot plug device in global array.
|
||||
@param Event The retuned event that invoke this function.
|
||||
@param Event The returned event that invoke this function.
|
||||
|
||||
@return Status of create event invoken.
|
||||
@return Status of create event.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
|
|
@ -188,7 +188,7 @@ IsSHPC (
|
|||
|
||||
@param[in] PciIoDevice The device being checked.
|
||||
|
||||
@retval TRUE PciIoDevice is a PCIe port that accepts a hotplugged device.
|
||||
@retval TRUE PciIoDevice is a PCIe port that accepts a hot-plugged device.
|
||||
@retval FALSE Otherwise.
|
||||
|
||||
**/
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
EFI PCI IO protocol functions implementation for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -1316,7 +1316,7 @@ CheckBarType (
|
|||
@param Operation Set or Disable.
|
||||
|
||||
@retval EFI_UNSUPPORTED If root bridge does not support change attribute.
|
||||
@retval EFI_SUCCESS Successfully set new attributs.
|
||||
@retval EFI_SUCCESS Successfully set new attributes.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
|
|
@ -1419,7 +1419,7 @@ SupportPaletteSnoopAttributes (
|
|||
|
||||
if (Temp == NULL) {
|
||||
//
|
||||
// If there is no VGA device on the segement, set
|
||||
// If there is no VGA device on the segment, set
|
||||
// this graphics card to decode the palette range
|
||||
//
|
||||
return EFI_SUCCESS;
|
||||
|
|
@ -1588,7 +1588,7 @@ PciIoAttributes (
|
|||
//
|
||||
// Just a trick for ENABLE attribute
|
||||
// EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
|
||||
// So, this logic doesn't confrom to UEFI spec, which should be removed.
|
||||
// So, this logic doesn't conform to UEFI spec, which should be removed.
|
||||
// But this trick logic is still kept for some binary drivers that depend on it.
|
||||
//
|
||||
if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {
|
||||
|
|
@ -1725,7 +1725,7 @@ PciIoAttributes (
|
|||
Command |= EFI_PCI_COMMAND_BUS_MASTER;
|
||||
}
|
||||
//
|
||||
// The upstream bridge should be also set to revelant attribute
|
||||
// The upstream bridge should be also set to relevant attribute
|
||||
// expect for IO, Mem and BusMaster
|
||||
//
|
||||
UpStreamAttributes = Attributes &
|
||||
|
|
@ -1911,7 +1911,7 @@ PciIoGetBarAttributes (
|
|||
|
||||
case PciBarTypePMem32:
|
||||
//
|
||||
// prefechable
|
||||
// prefetchable
|
||||
//
|
||||
Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
|
||||
//
|
||||
|
|
@ -1930,7 +1930,7 @@ PciIoGetBarAttributes (
|
|||
|
||||
case PciBarTypePMem64:
|
||||
//
|
||||
// prefechable
|
||||
// prefetchable
|
||||
//
|
||||
Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
|
||||
//
|
||||
|
|
@ -2042,7 +2042,7 @@ PciIoSetBarAttributes (
|
|||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
//
|
||||
// Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and
|
||||
// Attributes must be supported. Make sure the BAR range described by BarIndex, Offset, and
|
||||
// Length are valid for this PCI device.
|
||||
//
|
||||
NonRelativeOffset = *Offset;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
EFI PCI IO protocol functions declaration for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -527,7 +527,7 @@ CheckBarType (
|
|||
@param Operation Set or Disable.
|
||||
|
||||
@retval EFI_UNSUPPORTED If root bridge does not support change attribute.
|
||||
@retval EFI_SUCCESS Successfully set new attributs.
|
||||
@retval EFI_SUCCESS Successfully set new attributes.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PCI Rom supporting funtions implementation for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -604,7 +604,7 @@ RomDecode (
|
|||
//
|
||||
// Programe all upstream bridge
|
||||
//
|
||||
ProgrameUpstreamBridgeForRom(PciDevice, RomBar, TRUE);
|
||||
ProgramUpstreamBridgeForRom (PciDevice, RomBar, TRUE);
|
||||
|
||||
//
|
||||
// Setting the memory space bit in the function's command register
|
||||
|
|
@ -621,7 +621,7 @@ RomDecode (
|
|||
//
|
||||
// Destroy the programmed bar in all the upstream bridge.
|
||||
//
|
||||
ProgrameUpstreamBridgeForRom(PciDevice, RomBar, FALSE);
|
||||
ProgramUpstreamBridgeForRom (PciDevice, RomBar, FALSE);
|
||||
|
||||
//
|
||||
// disable rom decode
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PCI Rom supporting funtions declaration for PCI Bus module.
|
||||
PCI Rom supporting functions declaration for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Power management support fucntions implementation for PCI Bus module.
|
||||
Power management support functions implementation for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Power management support fucntions delaration for PCI Bus module.
|
||||
Power management support functions declaration for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PCI resouces support functions implemntation for PCI Bus module.
|
||||
PCI resources support functions implementation for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -134,11 +134,11 @@ InsertResourceNode (
|
|||
|
||||
/**
|
||||
This routine is used to merge two different resource trees in need of
|
||||
resoure degradation.
|
||||
resource degradation.
|
||||
|
||||
For example, if an upstream PPB doesn't support,
|
||||
prefetchable memory decoding, the PCI bus driver will choose to call this function
|
||||
to merge prefectchable memory resource list into normal memory list.
|
||||
to merge prefetchable memory resource list into normal memory list.
|
||||
|
||||
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource
|
||||
type.
|
||||
|
|
@ -335,7 +335,7 @@ CalculateApertureIo16 (
|
|||
This function is used to calculate the resource aperture
|
||||
for a given bridge device.
|
||||
|
||||
@param Bridge PCI resouce node for given bridge device.
|
||||
@param Bridge PCI resource node for given bridge device.
|
||||
|
||||
**/
|
||||
VOID
|
||||
|
|
@ -413,7 +413,7 @@ CalculateResourceAperture (
|
|||
}
|
||||
|
||||
/**
|
||||
Get IO/Memory resource infor for given PCI device.
|
||||
Get IO/Memory resource info for given PCI device.
|
||||
|
||||
@param PciDev Pci device instance.
|
||||
@param IoNode Resource info node for IO .
|
||||
|
|
@ -832,7 +832,7 @@ CreateResourceMap (
|
|||
);
|
||||
|
||||
//
|
||||
// Recursively create resouce map on this bridge
|
||||
// Recursively create resource map on this bridge
|
||||
//
|
||||
CreateResourceMap (
|
||||
Temp,
|
||||
|
|
@ -1195,10 +1195,10 @@ BridgeSupportResourceDecode (
|
|||
This function is used to program the resource allocated
|
||||
for each resource node under specified bridge.
|
||||
|
||||
@param Base Base address of resource to be progammed.
|
||||
@param Base Base address of resource to be programmed.
|
||||
@param Bridge PCI resource node for the bridge device.
|
||||
|
||||
@retval EFI_SUCCESS Successfully to program all resouces
|
||||
@retval EFI_SUCCESS Successfully to program all resources
|
||||
on given PCI bridge device.
|
||||
@retval EFI_OUT_OF_RESOURCES Base is all one.
|
||||
|
||||
|
|
@ -1257,8 +1257,8 @@ ProgramResource (
|
|||
/**
|
||||
Program Bar register for PCI device.
|
||||
|
||||
@param Base Base address for PCI device resource to be progammed.
|
||||
@param Node Point to resoure node structure.
|
||||
@param Base Base address for PCI device resource to be programmed.
|
||||
@param Node Point to resource node structure.
|
||||
|
||||
**/
|
||||
VOID
|
||||
|
|
@ -1354,8 +1354,8 @@ ProgramBar (
|
|||
/**
|
||||
Program IOV VF Bar register for PCI device.
|
||||
|
||||
@param Base Base address for PCI device resource to be progammed.
|
||||
@param Node Point to resoure node structure.
|
||||
@param Base Base address for PCI device resource to be programmed.
|
||||
@param Node Point to resource node structure.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
|
|
@ -1438,10 +1438,10 @@ ProgramVfBar (
|
|||
}
|
||||
|
||||
/**
|
||||
Program PCI-PCI bridge apperture.
|
||||
Program PCI-PCI bridge aperture.
|
||||
|
||||
@param Base Base address for resource.
|
||||
@param Node Point to resoure node structure.
|
||||
@param Node Point to resource node structure.
|
||||
|
||||
**/
|
||||
VOID
|
||||
|
|
@ -1457,7 +1457,7 @@ ProgramPpbApperture (
|
|||
Address = 0;
|
||||
//
|
||||
// If no device resource of this PPB, return anyway
|
||||
// Apperture is set default in the initialization code
|
||||
// Aperture is set default in the initialization code
|
||||
//
|
||||
if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {
|
||||
//
|
||||
|
|
@ -1649,13 +1649,13 @@ ProgramPpbApperture (
|
|||
/**
|
||||
Program parent bridge for Option Rom.
|
||||
|
||||
@param PciDevice Pci deivce instance.
|
||||
@param OptionRomBase Base address for Optiona Rom.
|
||||
@param PciDevice Pci device instance.
|
||||
@param OptionRomBase Base address for Option Rom.
|
||||
@param Enable Enable or disable PCI memory.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ProgrameUpstreamBridgeForRom (
|
||||
ProgramUpstreamBridgeForRom (
|
||||
IN PCI_IO_DEVICE *PciDevice,
|
||||
IN UINT32 OptionRomBase,
|
||||
IN BOOLEAN Enable
|
||||
|
|
@ -1682,7 +1682,7 @@ ProgrameUpstreamBridgeForRom (
|
|||
Node.Offset = 0;
|
||||
|
||||
//
|
||||
// Program PPB to only open a single <= 16MB apperture
|
||||
// Program PPB to only open a single <= 16MB aperture
|
||||
//
|
||||
if (Enable) {
|
||||
//
|
||||
|
|
@ -1763,7 +1763,7 @@ InitializeResourcePool (
|
|||
}
|
||||
|
||||
/**
|
||||
Destory given resource tree.
|
||||
Destroy given resource tree.
|
||||
|
||||
@param Bridge PCI resource root node of resource tree.
|
||||
|
||||
|
|
@ -1820,7 +1820,7 @@ ResourcePaddingForCardBusBridge (
|
|||
|
||||
//
|
||||
// Memory Base/Limit Register 0
|
||||
// Bar 1 denodes memory range 0
|
||||
// Bar 1 decodes memory range 0
|
||||
//
|
||||
Node = CreateResourceNode (
|
||||
PciDev,
|
||||
|
|
@ -1838,7 +1838,7 @@ ResourcePaddingForCardBusBridge (
|
|||
|
||||
//
|
||||
// Memory Base/Limit Register 1
|
||||
// Bar 2 denodes memory range1
|
||||
// Bar 2 decodes memory range1
|
||||
//
|
||||
Node = CreateResourceNode (
|
||||
PciDev,
|
||||
|
|
@ -1856,7 +1856,7 @@ ResourcePaddingForCardBusBridge (
|
|||
|
||||
//
|
||||
// Io Base/Limit
|
||||
// Bar 3 denodes io range 0
|
||||
// Bar 3 decodes io range 0
|
||||
//
|
||||
Node = CreateResourceNode (
|
||||
PciDev,
|
||||
|
|
@ -1874,7 +1874,7 @@ ResourcePaddingForCardBusBridge (
|
|||
|
||||
//
|
||||
// Io Base/Limit
|
||||
// Bar 4 denodes io range 0
|
||||
// Bar 4 decodes io range 0
|
||||
//
|
||||
Node = CreateResourceNode (
|
||||
PciDev,
|
||||
|
|
@ -1978,7 +1978,7 @@ ProgramP2C (
|
|||
|
||||
} else {
|
||||
//
|
||||
// Set pre-fetchable bit
|
||||
// Set prefetchable bit
|
||||
//
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
|
|
@ -2048,7 +2048,7 @@ ProgramP2C (
|
|||
} else {
|
||||
|
||||
//
|
||||
// Set pre-fetchable bit
|
||||
// Set prefetchable bit
|
||||
//
|
||||
PciIo->Pci.Read (
|
||||
PciIo,
|
||||
|
|
@ -2181,7 +2181,7 @@ ApplyResourcePadding (
|
|||
if (Ptr->AddrSpaceGranularity == 32) {
|
||||
|
||||
//
|
||||
// prefechable
|
||||
// prefetchable
|
||||
//
|
||||
if (Ptr->SpecificFlag == 0x6) {
|
||||
if (Ptr->AddrLen != 0) {
|
||||
|
|
@ -2204,7 +2204,7 @@ ApplyResourcePadding (
|
|||
}
|
||||
|
||||
//
|
||||
// Non-prefechable
|
||||
// Non-prefetchable
|
||||
//
|
||||
if (Ptr->SpecificFlag == 0) {
|
||||
if (Ptr->AddrLen != 0) {
|
||||
|
|
@ -2230,7 +2230,7 @@ ApplyResourcePadding (
|
|||
if (Ptr->AddrSpaceGranularity == 64) {
|
||||
|
||||
//
|
||||
// prefechable
|
||||
// prefetchable
|
||||
//
|
||||
if (Ptr->SpecificFlag == 0x6) {
|
||||
if (Ptr->AddrLen != 0) {
|
||||
|
|
@ -2253,7 +2253,7 @@ ApplyResourcePadding (
|
|||
}
|
||||
|
||||
//
|
||||
// Non-prefechable
|
||||
// Non-prefetchable
|
||||
//
|
||||
if (Ptr->SpecificFlag == 0) {
|
||||
if (Ptr->AddrLen != 0) {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
PCI resouces support functions declaration for PCI Bus module.
|
||||
PCI resources support functions declaration for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -82,11 +82,11 @@ InsertResourceNode (
|
|||
|
||||
/**
|
||||
This routine is used to merge two different resource trees in need of
|
||||
resoure degradation.
|
||||
resource degradation.
|
||||
|
||||
For example, if an upstream PPB doesn't support,
|
||||
prefetchable memory decoding, the PCI bus driver will choose to call this function
|
||||
to merge prefectchable memory resource list into normal memory list.
|
||||
to merge prefetchable memory resource list into normal memory list.
|
||||
|
||||
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource
|
||||
type.
|
||||
|
|
@ -121,7 +121,7 @@ CalculateApertureIo16 (
|
|||
This function is used to calculate the resource aperture
|
||||
for a given bridge device.
|
||||
|
||||
@param Bridge PCI resouce node for given bridge device.
|
||||
@param Bridge PCI resource node for given bridge device.
|
||||
|
||||
**/
|
||||
VOID
|
||||
|
|
@ -130,7 +130,7 @@ CalculateResourceAperture (
|
|||
);
|
||||
|
||||
/**
|
||||
Get IO/Memory resource infor for given PCI device.
|
||||
Get IO/Memory resource info for given PCI device.
|
||||
|
||||
@param PciDev Pci device instance.
|
||||
@param IoNode Resource info node for IO .
|
||||
|
|
@ -175,8 +175,7 @@ CreateResourceNode (
|
|||
);
|
||||
|
||||
/**
|
||||
This function is used to extract resource request from
|
||||
IOV VF device node list.
|
||||
This function is used to create a IOV VF resource node.
|
||||
|
||||
@param PciDev Pci device instance.
|
||||
@param Length Length of Io/Memory resource.
|
||||
|
|
@ -185,7 +184,7 @@ CreateResourceNode (
|
|||
@param ResType Type of resource: IO/Memory.
|
||||
@param ResUsage Resource usage.
|
||||
|
||||
@return PCI resource node created for given PCI device.
|
||||
@return PCI resource node created for given VF PCI device.
|
||||
NULL means PCI resource node is not created.
|
||||
|
||||
**/
|
||||
|
|
@ -285,10 +284,10 @@ BridgeSupportResourceDecode (
|
|||
This function is used to program the resource allocated
|
||||
for each resource node under specified bridge.
|
||||
|
||||
@param Base Base address of resource to be progammed.
|
||||
@param Base Base address of resource to be programmed.
|
||||
@param Bridge PCI resource node for the bridge device.
|
||||
|
||||
@retval EFI_SUCCESS Successfully to program all resouces
|
||||
@retval EFI_SUCCESS Successfully to program all resources
|
||||
on given PCI bridge device.
|
||||
@retval EFI_OUT_OF_RESOURCES Base is all one.
|
||||
|
||||
|
|
@ -302,8 +301,8 @@ ProgramResource (
|
|||
/**
|
||||
Program Bar register for PCI device.
|
||||
|
||||
@param Base Base address for PCI device resource to be progammed.
|
||||
@param Node Point to resoure node structure.
|
||||
@param Base Base address for PCI device resource to be programmed.
|
||||
@param Node Point to resource node structure.
|
||||
|
||||
**/
|
||||
VOID
|
||||
|
|
@ -315,8 +314,8 @@ ProgramBar (
|
|||
/**
|
||||
Program IOV VF Bar register for PCI device.
|
||||
|
||||
@param Base Base address for PCI device resource to be progammed.
|
||||
@param Node Point to resoure node structure.
|
||||
@param Base Base address for PCI device resource to be programmed.
|
||||
@param Node Point to resource node structure.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
|
|
@ -326,10 +325,10 @@ ProgramVfBar (
|
|||
);
|
||||
|
||||
/**
|
||||
Program PCI-PCI bridge apperture.
|
||||
Program PCI-PCI bridge aperture.
|
||||
|
||||
@param Base Base address for resource.
|
||||
@param Node Point to resoure node structure.
|
||||
@param Node Point to resource node structure.
|
||||
|
||||
**/
|
||||
VOID
|
||||
|
|
@ -341,13 +340,13 @@ ProgramPpbApperture (
|
|||
/**
|
||||
Program parent bridge for Option Rom.
|
||||
|
||||
@param PciDevice Pci deivce instance.
|
||||
@param OptionRomBase Base address for Optiona Rom.
|
||||
@param PciDevice Pci device instance.
|
||||
@param OptionRomBase Base address for Option Rom.
|
||||
@param Enable Enable or disable PCI memory.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ProgrameUpstreamBridgeForRom (
|
||||
ProgramUpstreamBridgeForRom (
|
||||
IN PCI_IO_DEVICE *PciDevice,
|
||||
IN UINT32 OptionRomBase,
|
||||
IN BOOLEAN Enable
|
||||
|
|
@ -382,7 +381,7 @@ InitializeResourcePool (
|
|||
);
|
||||
|
||||
/**
|
||||
Destory given resource tree.
|
||||
Destroy given resource tree.
|
||||
|
||||
@param Bridge PCI resource root node of resource tree.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Set up ROM Table for PCI Bus module.
|
||||
|
||||
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -23,9 +23,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|||
@param Bus Bus NO of PCI space.
|
||||
@param Dev Dev NO of PCI space.
|
||||
@param Func Func NO of PCI space.
|
||||
@param RomImage Option ROM buffer.
|
||||
@param RomSize Size of Option ROM buffer.
|
||||
|
||||
@param RomImage Option Rom buffer.
|
||||
@param RomSize Size of Option Rom buffer.
|
||||
**/
|
||||
VOID
|
||||
PciRomAddImageMapping (
|
||||
|
|
|
|||
Loading…
Reference in New Issue